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Design Engineer

Location:
Scottsdale, Arizona, United States
Posted:
April 09, 2018

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Resume:

Vandana Raj Therveetil

+1-602-***-****, ac4220@r.postjobfree.com

Scottsdale, Arizona

Seeking ASIC/Physical Design Engineer position in Semiconductor industry with a technology driven organization. PROFESSIONAL ABRIDGEMENT

Strong VLSI professional with around 3 years of experience in Electronic Design Automation Industry. Good hands on experience in Synthesis and Physical Design tools. Good understanding of VLSI design flow and worked intensively on Design flow validation. First rank holder in MTech VLSI from Amrita School of Engineering.

Thorough knowledge of ASIC VLSI flow from RTL to GDSII including Synthesis, Floor planning, Power planning, Placement, Clock tree Synthesis, Routing.

Excellent skills in establishing regression testing flows and test plan development & validation across multiple implementation tools. New feature testing of electronic design automation (EDA) tools

Strong expertise with industry-standard circuit design flow methodologies. Demonstrated excellence in large complex high value methodology projects involving multiple vendors. Debugging design issues, re-testing and reporting.

Insightful experience in SoC and flat design implementation and their validation.

Proficient with Synopsys Galaxy Implementation Platform tools - Design Compiler, IC Compiler, IC Compiler II, PT

Sound knowledge about Front End and Physical Design Implementation, Static Timing Analysis and Unified Power Format (Low Power Designs)

Flow cleanup of lower technology nodes (45nm,28 nm,16nm,7nm). Experience in resolving various Block level. Chip level timing issues, power, routability etc.

Strong understanding of digital & analog design, CMOS fundamentals, CMOS process flow and semiconductor device physics.

Superior written and oral communication skills. Good interpersonal skills & greatly appreciated and acknowledged by the customers and management.

SKILLS and TOOLS

o Programming skills : VERILOG, VHDL, TCL script, Perl, UNIX, C programming, Python o Software exposure : MATLAB, MPLAB, ModelSim, Xilinx (FPGA programming), VCS,SPICE o Cadence tools : Virtuoso, Schematic Editor, Encounter SoC, NCSim o Synopsys tools : Design Compiler, IC Compiler, IC Compiler II, Library Manager, PrimeTime, TETRAMAX Good understanding of Microprocessor, Microcontroller architecture and programming. CAREER HIGHLIGHTS

SYNOPSYS INDIA PVT Ltd.

Corporate Application Engineer II

Project : Development of QA & regression tests for 16.03,16.12 and 17.09 product releases. Period : Feb 2016 – Aug 2017

Business Unit : Design Group

Tools Used : Design Compiler, ICC II, Prime Time, Formality, DFT, TetraMax, StarRC Roles and responsibility:

Defined clear objectives & Scope of project. Good understanding of ASIC flow from RTL to GDS II. Evaluation of product releases on Flat, Hierarchical, UPF Based Low Power, MCMM & ECO based flows.

Implementing the Reference Methodology(RM) variable changes in latest product release to the available design suites. Test runs with alpha, beta builds to ensure the changes.

Defining the test plan with exit criteria. The tools which are covered as a part of these flows include Design Compiler, IC Compiler II, DFT Compiler, TetraMax, Formality, StarRC, Primetime. Focus was mainly on with Vandana Raj Therveetil

+1-602-***-****, ac4220@r.postjobfree.com

Scottsdale, Arizona

synthesis, formal equivalence, placement, optimization, low power checks, CTS, routing, crosstalk delay/noise analysis etc.

Submitting jobs in grid with the specified number of cores and hosts and continuous monitoring.

Reporting the stability issues, crashes and filing Cases or STARs in Synopsys’ technical support database whenever required and communicate with R&D.

Running the reporting utility (PRS) and generating the HTMLs containing the required QoR (Quality of Results) like routeability, timing, power, runtime, memory, area.

Analyzing the improvement or degradation on per testcase basis (Outliers) and determining the root causes.

Created 3 flow suites for the team: HPLP (High performance Low Power), Congestion reduction flow, Area reduction flow considering the flow specific app options.

Conclude & Summarize with useful inputs.

Mentored new interns joining the team.

Key Accomplishments

Developed Test Plan document.

Consolidated the results from experiments and sharing with stake holders.

Complied testing reports with recommendations and conclusions.

Was able to complete the project tasks as planned. Project : Implementation of methodological flows based on internal Synopsys synthesis tool under development

Period : Dec 2016 – Aug 2017

Business Unit : Design Group

Tools Used : Synthesis tool under development, Design Compiler, ICC II, Prime Time, Formality, DFT, TetraMax Description : The company is about to launch a new synthesis tool which is an engineering effort to increase the runtime speed and capacity of DC in the ICC2 database. Implementing methodological flows based on new tool & Comparing the Quality of results.

Roles and responsibility:

Participated effectively in Project discussions on Test planning, cost-of-quality.

Communicating with the global team and Development team to understand the latest developments in tool and availability of testcases and getting ownership of customer owned designs.

Ported the various lower node (7nm,16nm,28nm,45nm) testcases in DC-ICCII flow using migration assistant utility. to the environment adaptable for the new tool.

Implemented methodology to test the results. Design issues were prioritized based on the categories.

Ran Sanity checks and consistency checks on the test suite. Formality and DFT consistency was also verified. Regular discussion with Signoff team on day to day development of testcase.

Reporting the stability issues and crashes and filing Cases or STARs in Synopsys’ technical support database whenever required.

Regression testing on available Beta versions were done as a part of new feature testing of tool. Key Accomplishments

Deliverable testcases handed over to Signoff team on time & got appreciation from higher authorities

Pursued a global perspective on working in the internal SNPS tool Project : Quality work on run time reduction of customer owned NVIDIA designs and routeability issues of AMD design.

Period : June 2016 – March2017

Business Unit : Design Group

Tools Used : ICC II, PrimeTime

Vandana Raj Therveetil

+1-602-***-****, ac4220@r.postjobfree.com

Scottsdale, Arizona

Roles and responsibility:

Ownership of the customer designs.

To understand customer runset on attaining good QoR.

Tried different methodology on testcases for attempting flow changes according to the run time needs.

Identification of root causes and tried different tool variable settings on resolving the routeability issues.

Reproducing results, stability checks and reports. Key Accomplishments

• Identified root cause of routeability issues and reported to the team.

• Able to achieve good insight into customer flow. Able to drive results on time. Project : Test power analysis and their optimization techniques (low power testing) Associate Corporate Application Engineer

Period : January 2015 – July 2015

Business Unit : Design Group

Tools Used : DC, ICC, DFT, TetraMax, PTPX, VCS

Developed a flow to estimate Test power which involved test vector generation for 90nm chip, simulation of Test vectors for the activity, power estimation and dynamic power analysis. Got a good understanding of VLSI design flow.

Duties as Associate Corporate Application Engineer Period : January 2015 – Feb 2016

Created lot of clean potential NDM database from the available LEFs and dbs using the ICC II Library Manager. Good understanding of potential problems that can be hit and their respective solutions.

Handled classic CTS and CCD (Concurrent Clock Data) methodological flow validation of IC compiler.

Good exposure to low power designs. Worked on Golden UPF and UPF’ designs.

Developed a reporting utility for DC-ICC different UPF variants flat, hierarchical suites using PERL.

Developed a new test suite by porting the free access testcases from SYNOPSYS CRM data search which had NDM models available. Adapted them to Synopsys inhouse SMART team Cache. Also ported inhouse RTL designs.

Customer 7nm Library Validation for routeability was done on a regular basis with every new build release.

Worked on some multi Vth (threshold voltage) designs and their power analysis.

Provided technical assistance in resolving customer issues that needed a deeper understanding of the tools.

Attended Customer Training sessions on Design Compiler, IC compiler, ICC II, DFT, TetraMax, PrimeTime, PTSI, Low power Synthesis & Physical Design, Formality.

Hands on experience in SPICE simulations.

Academia

Sl.N Course Completion Major Address Marks Obtained 1

Master of

Technology

(MTech)

Sep 2015 VLSI Design

AMRITA School of Engineering,

Amritapuri, Vallikavu, Kerala,

India

9.52 (GPA)

1st Rank with

Gold Medal

2

Bachelor of

Technology

(BTech)

Apr 2012

Electronics and

Communications

Engineering

Govt College of Engineering,

Kannur University,

Parassinikkadavu - Mayyil Road,

Dharmasala, Kannur, Kerala India

78%

3

Higher

Secondary

Education

Mar 2007 Science

Govt Brennen Higher Secondary

School, MG Rd, Palissery,

Thalassery, Kerala, India

96%

4

Secondary

Education

Mar 2005 All

Sacred Heart Girls High School

Palissery, Tellicherry Kerala, India

95%

Vandana Raj Therveetil

+1-602-***-****, ac4220@r.postjobfree.com

Scottsdale, Arizona

Master of Technology (MTech)

Course Projects

STANDARD CELL DESIGN

Design of various combinational, sequential standard Cells and their layout were done in Cadence

(Virtuoso).

SRAM CELL DESIGN

Design of conventional 1KB SRAM-6T in Cadence (Virtuoso) and layout were done. Noise margin analysis and SNM calculations were done

OPAMP DESIGN

Designed and analyzed a Single stage fully differential Telescopic Op-amp with a gain of 60 dB and 100MH bandwidth using cadence tools.

DIGITAL FIR FILTER DESIGN

Implementation of parallel and pipelined FIR Filter with given specifications using Mat Lab and Verilog code. Synthesis of filter with timing information, Scan Chain insertion, Place & Route of synthesized netlists. The filter was implemented in Verilog and verified against the vectors generated using MATLAB

MULTIPLIER DESIGN

32bx32 bit Multipliers based on booth encoding, modified booth encoding, and canonic signed digit based encoding are implemented using Verilog. Wallace tree adder and Vector Merging Adders are used for combining the partial products to enhance the speed. The multipliers were synthesized and implemented using NanGate 45nm Open Cell Library.

Publications

Springer AISC series-Design and implementation of 270 tap fir filter.

Springer AISC series-Implementation of 18-bit high speed binary multipliers Bachelor of Technology (BTech)

Course Projects

VIDEO PIRACY ERADICATION TECHNIQUES

In VPET technology we designed a complete complex system where concept of advanced frequency domain analysis of digital content is utilized to embed a secret information into the video file in our own idea of encryption at spectral level to encode a code in video.

UNINTERRUPTED POWER SUPPLY

Trainings Underdone

Attended the training course on FPGA at IIST, Trivandrum

Attended the Industrial training course on ‘Telecom Technology’ conducted by BSNL Kannur



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