| Distance: | Resume alert | Resumes 21 - 30 of 4119 |
High School Verification Engineer
Bengaluru, Karnataka, India
... PROFESSIONAL TRAINING Advanced VLSI Design and Verification JUNE 2023 - FEBURARY 2024. Maven Silicon VLSI Training Center, Bangalore. TECHNICAL SKILLS Digital Electronics Verilog HDL C Programming Basics Linux Listening to music Playing Kabaddi ... - 2024 Oct 24
... PROFESSIONAL TRAINING Advanced VLSI Design and Verification JUNE 2023 - FEBURARY 2024. Maven Silicon VLSI Training Center, Bangalore. TECHNICAL SKILLS Digital Electronics Verilog HDL C Programming Basics Linux Listening to music Playing Kabaddi ... - 2024 Oct 24
Design Engineer Physical
Bengaluru, Karnataka, India
KEERTHANA CV PHYSICAL DESIGN ENGINEER +917********* *****************@*****.*** Keerthana CV To obtain a career in VLSI Industry as a Physical Design Engineer, Where i can contribute my skills for organization’s success and improving my technical ... - 2024 Oct 24
KEERTHANA CV PHYSICAL DESIGN ENGINEER +917********* *****************@*****.*** Keerthana CV To obtain a career in VLSI Industry as a Physical Design Engineer, Where i can contribute my skills for organization’s success and improving my technical ... - 2024 Oct 24
Physical Design Entry Level
Bengaluru, Karnataka, India
... PROFESSIONAL TRAINING: An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from SILICONUS Pvt.Ltd Bangalore from APRIL 2024 to SEPTEMBER 2024. Physical design PNR Technology / Metallayers TSMC 28nm / 9 Tool Cadence - Innovus Instance count 56k ... - 2024 Oct 24
... PROFESSIONAL TRAINING: An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from SILICONUS Pvt.Ltd Bangalore from APRIL 2024 to SEPTEMBER 2024. Physical design PNR Technology / Metallayers TSMC 28nm / 9 Tool Cadence - Innovus Instance count 56k ... - 2024 Oct 24
Design verification trainee
Cuddalore, Tamil Nadu, India
... Design Verification Trainee In this training period I have learned about various design methodologies used in VLSI design, such as RTL design, logic synthesis, ASIC Verification. In addition, master the concepts of RTL coding languages and verification ... - 2024 Oct 24
... Design Verification Trainee In this training period I have learned about various design methodologies used in VLSI design, such as RTL design, logic synthesis, ASIC Verification. In addition, master the concepts of RTL coding languages and verification ... - 2024 Oct 24
Head of Business
Pune, Maharashtra, India
... Engineering (Kubernetes, Docker, Jenkins), Full-Stack Development (React.js, Node.js, Angular, Vue.js), Semiconductor Engineering (VLSI Design, ASIC/FPGA, Verilog, SystemVerilog), AI-driven Chip Design, IT-OT Convergence (Operational Technology and ... - 2024 Oct 10
... Engineering (Kubernetes, Docker, Jenkins), Full-Stack Development (React.js, Node.js, Angular, Vue.js), Semiconductor Engineering (VLSI Design, ASIC/FPGA, Verilog, SystemVerilog), AI-driven Chip Design, IT-OT Convergence (Operational Technology and ... - 2024 Oct 10
Pcb Design High School
Bengaluru, Karnataka, India
... “WIRELESS FIDELITY” PCB design ACHIEVEMENTS: • Completed my internship cum training program on “ PCB DESIGN AND BASICS OF VLSI DESIGN” for 4 weeks at RARO TECHNOLOGIES PVT LTD • Serviced as NSS Volunteer for 2 years JOB EXPERIENCE : 1. Worked as ... - 2024 Oct 03
... “WIRELESS FIDELITY” PCB design ACHIEVEMENTS: • Completed my internship cum training program on “ PCB DESIGN AND BASICS OF VLSI DESIGN” for 4 weeks at RARO TECHNOLOGIES PVT LTD • Serviced as NSS Volunteer for 2 years JOB EXPERIENCE : 1. Worked as ... - 2024 Oct 03
Hr Manager
Chennai, Tamil Nadu, India
... WORK EXPERIENCE EDUCATION Master of Engineering in VLSI Design PSN Technology and Institute, Anna University Aug 2018 - April 2020 Developed and implemented strategic HR initiatives and policies to align with organizational goals. Fostered a diverse ... - 2024 Sep 03
... WORK EXPERIENCE EDUCATION Master of Engineering in VLSI Design PSN Technology and Institute, Anna University Aug 2018 - April 2020 Developed and implemented strategic HR initiatives and policies to align with organizational goals. Fostered a diverse ... - 2024 Sep 03
Data entry operator
Coimbatore, Tamil Nadu, India
... AREA OF INTREST Digital Electronics VLSI PROJECT WORKS SMS Dustpin Informer Voice Controlled Robert Using Artificial Intelligence WORK EXPERINCE Working at “Mega Info Tech” Gobichettipalayam in Erode(Dt).One year Working “XML” process & QC Project. ... - 2024 Aug 20
... AREA OF INTREST Digital Electronics VLSI PROJECT WORKS SMS Dustpin Informer Voice Controlled Robert Using Artificial Intelligence WORK EXPERINCE Working at “Mega Info Tech” Gobichettipalayam in Erode(Dt).One year Working “XML” process & QC Project. ... - 2024 Aug 20
Qa Engineer Automation
Pune, Maharashtra, India
... 2024 – Present Encora (Excellarate), Pune Junior QA Engineer Dec 2021 – Jan 2024 Encora (Excellarate), Pune Education ME in VLSI & ES (2018-2021) Pune University BE in E&TC (2012-2015) Pune University Diploma in Industrial Electronic(2009-2012) ... - 2024 Aug 06
... 2024 – Present Encora (Excellarate), Pune Junior QA Engineer Dec 2021 – Jan 2024 Encora (Excellarate), Pune Education ME in VLSI & ES (2018-2021) Pune University BE in E&TC (2012-2015) Pune University Diploma in Industrial Electronic(2009-2012) ... - 2024 Aug 06
Front End Embedded Software
India
... Recently I qualified courses on VLSI Signal Processing, “CMOS Digital VLSI Design, and Hardware Modelling using Verilog from IIT’s. • I have been Principal/Director at LIET, Alwar, IIST, Indore, AIT Alwar and SBMN Engineering College, Rohtak. • I ... - 2024 Jul 21
... Recently I qualified courses on VLSI Signal Processing, “CMOS Digital VLSI Design, and Hardware Modelling using Verilog from IIT’s. • I have been Principal/Director at LIET, Alwar, IIST, Indore, AIT Alwar and SBMN Engineering College, Rohtak. • I ... - 2024 Jul 21