Design verification trainee

**/****

**/****

**/****

**/****

Aiming to be associated with a progressive organization that gives me the scope to apply my knowledge and skills, to involve as a part of the team that dynamically works towards the growth of the organization. Design Verification Trainee

In this training period I have learned about various design methodologies used in VLSI design, such as RTL design, logic synthesis, ASIC Verification. In addition, master the concepts of RTL coding languages and verification methodologies. Besides got exposure to Synopsys tool used in VLSI design flow. Had hands on experience in The characteristic features of training includes : Project specification analysis

design verification plan

Creating testbench architecture

Implementing the coverage model

Building top level verification environment

Generating the functional and Code coverage reports. Master of Engineering in VLSI design

CGPA - 8.0

Bachelor of Engineering in Electronics and Communication CGPA - 7.5

Higher Secondary Education

70%

Secondary School Of Education

92%

Phase I project in post-graduation

The focus of this Project is the actual implementation of Network Router and verifies the functionality of the three port router for network on chip using Hardware description language Verilog and execution is done in Modelsim. to view my

LinkedIn profile

805-***-**** *******************@*****.***

https://www.linkedin.com/in/nivetha-n-210123177

Synopsys Design Compiler.

Scan

- Digital design, RTL coding, ASIC verification methodologies, SV Assertions, Functional coverage.

- Synopsys DC, xilinx vivado, Modelsim.

- Verilog, Python, System Verilog, UVM - RAL model and TLM. 09/2023 - 07/2024

Phase II project in post-graduation

This project focus on the synthesis and implementation of on chip clock randomisation in AES crypto processor using Hardware description language Verilog executed in xilinx vivado and emulation is done using Nexys 4 DDR FPGA board. Mini Project in post-graduation

The smart door system is a project that is aimed at improving the security system of our locks especially the door ways. Implemented the system schematic on the Proteus EDA and simulated to ensure that it is functioning as expected. The simulation process involves the use of a program to run the microcontroller that acts as the control system of the whole project. Code execution is done in KEIL IDE. Throughout this immersive introductory course, I've delved deep into the fundamental differences between ASIC and FPGA, Gaining a comprehensive understanding of the intricate SoC basics. This course explain the role of HDL in design entry and verification for FPGA and ASICs. I explored the fundamentals of python and learnt about python programming using jupyter notebook. Learning outcomes of this workshop includes RTL Design overview ; Logic synthesis concept and optimization; Input files for each stages; Overview of PDK files; Comparison of pre synthesis and post synthesis simulation ; Partitioning ; Physical Verification overview.

RTL Simulation using VCS/Verdi

Basic linux commands

Synthesis of RTL using DC (Design Compiler)

Floor planning, Power planning, Clock Tree Synthesis, PnR using ICCII. Static Timing analysis using Prime Time.

This workshop gives hands-on experience on following tools - Name : : Nivetha N

D.O.B : : 16/07/1999

Gender : Female

Nationality : Indian

Blood group : A1+ve

Father Name : Nadanasekar P

Mother Name : : Jaya J

Address : Chidambaram - Tamilnadu

VCS/Verdi, DC, ICC2, Prime Time with 28nm technology.

Contact this candidate