| Distance: | Resume alert | Resumes 1 - 10 of 4120 |
Design Engineer Rtl
Hyderabad, Telangana, India
... Tech Mahindra, Bangalore Associate Engineer (VLSI) (Feb 2022 - March 2023) Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL. Developed and verified FIFO designs using System Verilog testbenches. Worked on AMBA protocols ... - Jun 10
... Tech Mahindra, Bangalore Associate Engineer (VLSI) (Feb 2022 - March 2023) Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL. Developed and verified FIFO designs using System Verilog testbenches. Worked on AMBA protocols ... - Jun 10
Senior Engineer Power Supply
Hyderabad, Telangana, India
... VLSI Hardware design course and training in Fronyn Technologies, Hyderabad. Internship in “VISAKHAPATNAM STEEL PLANT” for Two weeks in June 2015. “Industrial Training” on “DATA ANALYSIS” In “EFFTRONICS SYSTEMS PVT.LTD” from January to February 2016. ... - May 29
... VLSI Hardware design course and training in Fronyn Technologies, Hyderabad. Internship in “VISAKHAPATNAM STEEL PLANT” for Two weeks in June 2015. “Industrial Training” on “DATA ANALYSIS” In “EFFTRONICS SYSTEMS PVT.LTD” from January to February 2016. ... - May 29
Asic Design Verification Engineer
Vadodara, Gujarat, India
... C, C++, Assembly (8086) Bus Protocols Known: AMBA AXI 4.0 Knowledge of cores& CPUs: ARM cores& CPUs (ARM-v7A, ARM-v8A), Cortex-A9 Memory Coherence protocols: Snoop Based (MESI, MOSI, and MOESI), Directory Based VLSI Experience: Parul University. ... - Apr 28
... C, C++, Assembly (8086) Bus Protocols Known: AMBA AXI 4.0 Knowledge of cores& CPUs: ARM cores& CPUs (ARM-v7A, ARM-v8A), Cortex-A9 Memory Coherence protocols: Snoop Based (MESI, MOSI, and MOESI), Directory Based VLSI Experience: Parul University. ... - Apr 28
Technical Writer Lead
Pune, Maharashtra, India
... Electronics in specialization with VLSI Design from Andhra University in 2012. Languages • English • Telugu • Kannada • Hindi - Apr 25
... Electronics in specialization with VLSI Design from Andhra University in 2012. Languages • English • Telugu • Kannada • Hindi - Apr 25
C++ Ms Sql
Pollachi, Tamil Nadu, India
... Educational Qualification Completed my Master of Engineering in VLSI DESIGN in the year 2014. Completed my Bachelor of Engineering in Electronics and Communication Engineering in the year 2012. Completed my Higher Secondary in the year 2008. ... - Apr 15
... Educational Qualification Completed my Master of Engineering in VLSI DESIGN in the year 2014. Completed my Bachelor of Engineering in Electronics and Communication Engineering in the year 2012. Completed my Higher Secondary in the year 2008. ... - Apr 15
Sap Hana Change Management
Hyderabad, Telangana, India
... FIELD:VLSI&Embedded System INSTITUTION:Malla Reddy Institute of Technology YEAR OF PASSING: 2014 PERCENTAGE:74.19% WORK EXPERIENCE ANZANI TRADING GROUP MAY 2022 TO PRESENT EDGEROCK SOFTWARE PRIVATE LIMITED DEC 2020 TO APRIL 2022 PROFILE SUMMARY: 1. ... - Apr 08
... FIELD:VLSI&Embedded System INSTITUTION:Malla Reddy Institute of Technology YEAR OF PASSING: 2014 PERCENTAGE:74.19% WORK EXPERIENCE ANZANI TRADING GROUP MAY 2022 TO PRESENT EDGEROCK SOFTWARE PRIVATE LIMITED DEC 2020 TO APRIL 2022 PROFILE SUMMARY: 1. ... - Apr 08
Quality Control Sap Pp
New Delhi, Delhi, India
... ●Participated in one day workshop on “VLSI and Its Application” held on March 24th, 2012 at Visveswaraya Group of Institutions campus, Dadri, G. B. Nagar. ●Participated in the events of Eclectic '12, the Technical Festival of VGI, held from 1st to ... - Mar 05
... ●Participated in one day workshop on “VLSI and Its Application” held on March 24th, 2012 at Visveswaraya Group of Institutions campus, Dadri, G. B. Nagar. ●Participated in the events of Eclectic '12, the Technical Festival of VGI, held from 1st to ... - Mar 05
Physical design engineer
Bengaluru, Karnataka, India
... • Have 1year internship experience on VLSI Physical design in Sion semiconductors, Bangalore from july 2019 to july 2020. • Have 1.2 years of experience as Associate analyst from GlobalLogic technologies from 2017 nov to 2018 dec. • Good knowledge ... - Feb 19
... • Have 1year internship experience on VLSI Physical design in Sion semiconductors, Bangalore from july 2019 to july 2020. • Have 1.2 years of experience as Associate analyst from GlobalLogic technologies from 2017 nov to 2018 dec. • Good knowledge ... - Feb 19
Be A Network Engineer
Odisha, India
... EXTRA QULIFICATION: - VLSI Training Central Tool Room & Training centre Bhubaneswar. PROFESSIONAL EXPERIENCE: CONTINUE: Joined at CHEMTROLS Industries Pvt.Ltd. Base at Bhubaneswar OPTCL (SLDC) post of SCADA and RTU Engineer on date 04 November 2022 ... - Feb 12
... EXTRA QULIFICATION: - VLSI Training Central Tool Room & Training centre Bhubaneswar. PROFESSIONAL EXPERIENCE: CONTINUE: Joined at CHEMTROLS Industries Pvt.Ltd. Base at Bhubaneswar OPTCL (SLDC) post of SCADA and RTU Engineer on date 04 November 2022 ... - Feb 12
Student
Hyderabad, Telangana, India
... TECHNICAL SKILLS Programming Languages: C, Java including basics of DSA Web Technologies: HTML, CSS, JavaScript Database: SQL INTERNSHIPS VLSI Short Term Internship-SkillDzire. May 2024 – June 2024 Gain exposure to the entire VLSI Design Process, ... - Feb 04
... TECHNICAL SKILLS Programming Languages: C, Java including basics of DSA Web Technologies: HTML, CSS, JavaScript Database: SQL INTERNSHIPS VLSI Short Term Internship-SkillDzire. May 2024 – June 2024 Gain exposure to the entire VLSI Design Process, ... - Feb 04