High School Verification Engineer
Resume:
TAMMINENI SHEKHAR REDDY
shekharreddytammineni@
gmail.com
CONTACT
Questa sim
Model Sim
VC Spy Glass
EDA TOOLS
HOBBIES
CAREER OBJECTIVE
EDUCATION
St. Ann's College of Engineering & Technology, Chirala. Uma Maheswara Junior College Ongole.
B. Tech (ECE) : 2019-2023 (7.3 CGPA)
INTERMEDIATE :2017-2019 (9.1 CGPA)
DESIGN AND VERIFICATION ENGINEER
SSC :2016-2017(8.8 CGPA)
Nagarjuna (E.M) High School Kandukur.
PROFESSIONAL TRAINING
Advanced VLSI Design and Verification
JUNE 2023 - FEBURARY 2024.
Maven Silicon VLSI Training Center, Bangalore.
TECHNICAL SKILLS
Digital Electronics
Verilog HDL
C Programming Basics
Linux
Listening to music
Playing Kabaddi
Photography
Travelling
Swimming
As a recent graduate, I possess up-to-date knowledge in VLSI, enabling me to address real-world challenges effectively. My goal is to evolve as a versatile professional engineer, dedicated to acquiring the expertise required to drive innovation and contribute to the growth of emerging engineering companies.
Rollapadu Ramalayam street
Dr.No:-3-50,Nellore,
Andhra Pradesh,523116
https://www.linkedin.com/in/
shekharreddy-tammineni-
303450235
STRENGTHS
DESIGN SKILLS
Digital Electronics : Combinational & Sequential circuits, FSM, Memories.
Verilog Programming : Data types, Operators, Processes, BA
& NBA, Delays in Verilog, begin - end & fork join blocks, looping & branching construct, System tasks & Functions, compiler directives, FSM coding, Synthesis issues, Races in simulation, pipelining RTL & TB Coding.
Advanced Verilog& Code Coverage: Generate block,
Continuous Procedural Assignments, Self-checking
testbench, Automatic Tasks Named Events and Stratified Event Queue.
Code Coverage: Statement and branch coverage, Condition
& Expression Coverage, Toggle & FSM Coverage.
Leadership
Time Management
Empathy
Contineous Learning
PROJECT
2.Router 1x3 – RTL Design and Verification
HDL: Verilog
TB Methodology: UVM
EDA Tools: Questa sim and ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.
LANGUAGE
English
Telugu
VERIFICATION SKILLS
Memories.
Interface - Mod Port and clocking
block.
Constraint Randomization.
Thread synchronization techniques.
Functional coverage.
2.System Verilog Assertions
3.UVM
UVM Objects & Components
UVM Factory & overriding methods
Stimulus Modelling
UVM Phases
UVM Configuration
TLM
UVM Sequence, virtual sequence &
sequencer.
ACADEMIC PROJECT
A Compact Planar Four port MIMO Antenna for 28/38
GHz milli-meter wave 5G Application.
Description : The antennas at each end of the
communications circuit are combined to minimize errors Creating multiple versions of the same signal provides more opportunities for data to reach the receiving antenna without being affected by fading, which increases the signal to noise ratio and error rate. By boosting the capacity of radio frequency (RF) systems. the antenna operating at 5G millimeter-wave candidate bands of 28 GHz and 38 GHz. Software: CST
Role : Team leader
DECLARATION
I would take this opportunity to thank you for going through my resume and above given information is true to the best of my knowledge.
Date:
Place: Bangalore Tammineni Shekhar Reddy
Types of assertions, assertion building
blocks, sequences with edge definitions
a logical relationship. Sequences with
different timing relationships. clock
defination, implication and repetion
operators, different sequence composi
-tions, inline and bindind assertions.
advanced SVA Features and assertion
coverage.
1.UART- IP Core – Verification
HVL : System Verilog
TB Methodology: UVM
Description: The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes – Simplex mode, Full Duplex mode and loopback mode.
1.System Verilog HVL
System UART supports both half-duplex and full-duplex communication. In half-duplex, devices take turns transmitting a nd receiving, while in full-duplex, both devices can transmit and receive simultaneously.
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