Design Engineer Physical
Resume:
KEERTHANA CV
PHYSICAL DESIGN ENGINEER
*****************@*****.***
Keerthana CV
To obtain a career in VLSI Industry as a Physical Design Engineer, Where i can contribute my skills for organization’s success and improving my technical ability while being resourceful, innovative and flexible.
Digital Electronics
Verilog
Logic Synthesis
Floor Planning & Placement
Routing
Clock Tree Synthesis
Static Timing Analysis
Signoff
Advanced Physical Design and Verification Course (August 2023 - Ongoing) Maven Silicon VLSI Training Institute, Bengaluru
B Tech Electronics and Communication (2019-2023)
Sree Narayana Guru College of engineering and Technology Payyanur
(2019-2023) (CGPA – 61.6%)
Higher Secondary Education (2017-2019)
GTHSS Kannur - Kerala State Board of Secondary Education. (65%) SSLC (2016-2017)
AHSS Azhikode - Kerala Board of Public Examination. (82%) HDL : Verilog
EDA Tool : Design Compiler, Prime Time, Fusion Compiler, Tanner Lab, ICC2 Domain : Physical Design flow including Floor Planning, Placement, CTS, Routing, STA and Signoff
Operating Systems : Windows and Linux
Version Control : GIT
Scripting Languages :TCL
Communication
Adaptability
Teamwork
Time Management
QUALIFICATION
Dance
Reading
Travelling
Music
Coordinated the National Level Technical Festival “UDBHAVA’23” at SNGCET Payyanur on April 2023
Volunteered “SATVI” cultural fest at SNGCET Payyanur on March 2022 and 2023 PnR Flow of RISC_V design
EDA:Design Compiler(DC),ICC2,Prime Time
• A RISC V design with 30 modules and 8K cells was given square floorplan to give equal horizontal and vertical routing resources to get a optimal area.
• Sourced all the constraints files separately to ensure efficiency of loading and for easy editing.
• Written a customized script for Power Grid generation keeping the DRCs into consideration.
• Faced routing congestions which were solved by creating blockages and ERCs were cleared by ECO techniques like resizing the cells and addition of buffers to improve timing. VLSI Project - Router 1x3
HDL : Verilog
EDA Tools : Design Compiler, Linting, Inserting DFT, Fusion Compiler, Prime Time. The Router 1x3 is designed and implemented using VLSI technology is to efficiently route 8 bits data packets from a single source to three different destination in a network. AUTOMATIC FISH AND PLANT CULTIVATION USING IoT
Team Size: Five members
My role: Lead the team, Lead Presenter, Research.
Tools: Atmega328, ORCAD CAPTURE, Node MCU, LDR sensor, Temperature and humidity sensor, two level water level sensor, current sensor, 5V Regulator, 12V ADC Adapter. Description: Our goal was to implement automation in agriculture and pisciculture which benefits the farmer and nature at the same time. The project focuses on the idea of combining fish and plant cultivation under the same roof. By using this technique we could save both time and space. The impure water from the aquarium is purified and given to the plant production part. Then the water will be purified again and supplied back to the fish tank saving the water and reducing human interference in the process.
I hereby declare that the above information provided is true to the best of my knowledge and belief.
Date :23/04/2024
Place : Bengaluru Keerthana CV
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