Verification Engineer Rtl Design

S D VIMALA

Design Verification RTL Design

Passionate about VLSI and seeking an opportunity to contribute my skills and knowledge in a challenging work environment. Strong understanding of digital design, verification, and synthesis. Detail-oriented and dedicated to delivering high-quality results. Striving to excel in the field of VLSI.

vimalasamandhawada@gmail

.com

938*******

linkedin.com/in/sdvimala

SKILLS

Verification Languages:

SystemVerilog, Verilog

Methodologies: UVM

Scripting Languages: Perl

Core Knowledge: Digital

Electronics

Analytical Skills: Strong

problem-solving abilities

Collaboration: Effective

communicator and team

player

LANGUAGES

Tamil

Native or Bilingual Proficiency

Telugu

Native or Bilingual Proficiency

English

Full Professional Proficiency

STRENGTH

Hard Worker

Good Team Player

Self Confidence

EDUCATION

Bachelor of Technology

Siddharth Institute of Engineering and Technology Puttur 07/2018 - 05/2022, 8.67(CGPA)

ECE

Intermediate

Sri Sai Jyothi Juniour College

2017 - 2018, 83%

MPC

SSC

Vasishta Vidhayalaya Nagari

2015 - 2016, 92%

PROJECTS

1. AHB to APB Bridge IP core Verification

at institute

Project Overview: Verified the functionality of an AHB to APB Bridge IP, which is used to interface between Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) in system-on-chip (SoC) designs. Testbench Development: Developed a SystemVerilog/UVM-based testbench to verify the AHB-to- APB bridge functionality.

2. Router 1 3 RTL Design and Verification

at Institute

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels. The block level structure for the design is architected. RTL is implemented using Verilog HDL. The class based verification environment is architected using UVM. The RTL module is verified using UVM TB. Functional and code coverage are generation for the RTL verification sign-off. The design is synthesized. PROFESSIONAL TRAINING

Maven Silicon VLSI Training Center

Advanced VLSI Design and Verification Trainee, Completed 6-months training design verification, focusing on industry-standard methodologies. Gained hands-on experience with simulation tools and test plan development. Covered key topics: verification methodologies, test planning, and execution. Gained proficiency in using simulation tools for design validation.

CERTIFICATES

Participated in Implementing Complex VLSI Application using Open Source EDA tools one week workshop.

Participated in Project Expo conducted as a part of department association,

“TARANG2K22”.

Participated in “Paper presentation” organized as a part of SIDDHARTH QUEST – 2K21 Branch

stream

Achievements/Tasks

Contact this candidate