| Resume alert | Resumes 111 - 120 of 450 |
Engineer Design
Fremont, CA
... Logic design, Analog circuit design, High bit rate digital (HDSL/HDSL2/SHDSL AND ADSL) line card design Designed CPLD for glue logic design using Verilog& VHDL . Schematic capture using ORCAD, VIEW-DRAW and CONCEPT HDL. During design phase, closely ... - 2017 Dec 13
... Logic design, Analog circuit design, High bit rate digital (HDSL/HDSL2/SHDSL AND ADSL) line card design Designed CPLD for glue logic design using Verilog& VHDL . Schematic capture using ORCAD, VIEW-DRAW and CONCEPT HDL. During design phase, closely ... - 2017 Dec 13
ASIC Verification Engineer, NVIDIA
San Jose, CA, 95134
... interface with DPI-C o Profiled the entire register-access and memory-access infrastructure at full-chip level using C++/System- Verilog to gauge scope for future optimizations and reduced runtime from days to hours o Detailed understanding of GPU ... - 2017 Dec 12
... interface with DPI-C o Profiled the entire register-access and memory-access infrastructure at full-chip level using C++/System- Verilog to gauge scope for future optimizations and reduced runtime from days to hours o Detailed understanding of GPU ... - 2017 Dec 12
Software engineer
Mountain View, CA
... ●Used ALTERA FPGA board and Quartus II software programmed in Verilog and C to implement signal transmission and communication between FPGA modules. ●Used JTAG protocol and USB connection to debug and verify the system. ●Implemented oscilloscope ... - 2017 Dec 11
... ●Used ALTERA FPGA board and Quartus II software programmed in Verilog and C to implement signal transmission and communication between FPGA modules. ●Used JTAG protocol and USB connection to debug and verify the system. ●Implemented oscilloscope ... - 2017 Dec 11
Design Electrical Engineering
San Jose, CA
... Proficient in Verilog, logic design principles, Static Timing Analysis, SoC design methodology, verification, C and Scripting. Familiar with Analog/Digital Design methodology. Comfortable with transistor level design. TECHNICAL SKILLS Skills ... - 2017 Dec 06
... Proficient in Verilog, logic design principles, Static Timing Analysis, SoC design methodology, verification, C and Scripting. Familiar with Analog/Digital Design methodology. Comfortable with transistor level design. TECHNICAL SKILLS Skills ... - 2017 Dec 06
Post Silicon Validation
San Jose, CA
... Technologies Programming: C/C++, Perl, Verilog, Assembly, VHDL. Technologies: OCP, Intel X86, MIPS. References Available upon request. - 2017 Nov 29
... Technologies Programming: C/C++, Perl, Verilog, Assembly, VHDL. Technologies: OCP, Intel X86, MIPS. References Available upon request. - 2017 Nov 29
Electrical Engineering Design
Cupertino, CA
... (Sept’16-May’17)-(Sept’17-Present) • Currently working on design and verification of endpoint block of PCI express gen3 using Verilog and UVM respectively • Designed and verified 1024 x 1024 Network on chip which tremendously improved speed of the ... - 2017 Nov 22
... (Sept’16-May’17)-(Sept’17-Present) • Currently working on design and verification of endpoint block of PCI express gen3 using Verilog and UVM respectively • Designed and verified 1024 x 1024 Network on chip which tremendously improved speed of the ... - 2017 Nov 22
Software State University
San Jose, CA
... Image Processing - Microprocessor & Microcontroller Competencies Programming Languages: C, C++, Python, CUDA C, C#, SQL, Verilog, Java Micro-controllers: FRDM KL25Z, LPC1758, Arduino UNO, Raspberry Pi 3, 8051, 8085/86, S3C6410, Jetson (TX2/TX1/TK1) ... - 2017 Nov 11
... Image Processing - Microprocessor & Microcontroller Competencies Programming Languages: C, C++, Python, CUDA C, C#, SQL, Verilog, Java Micro-controllers: FRDM KL25Z, LPC1758, Arduino UNO, Raspberry Pi 3, 8051, 8085/86, S3C6410, Jetson (TX2/TX1/TK1) ... - 2017 Nov 11
Design Electrical Engineering
Sunnyvale, CA
... of Engineering, Electrical Engineering GPA-3.7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design ... - 2017 Oct 26
... of Engineering, Electrical Engineering GPA-3.7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design ... - 2017 Oct 26
Agilent Ads, Ansys Hfss, Matlab,Auto CAD, Verilog Dhl
San Jose, CA
... Jan/ 2017 – May/ 2017 SKILLS&INTERESTS Agilent ADS, ANSYS HFSS, Matlab,Auto CAD, Microsoft Excel, Word, Powerpoint, Verilog DHL(in processing). - 2017 Oct 23
... Jan/ 2017 – May/ 2017 SKILLS&INTERESTS Agilent ADS, ANSYS HFSS, Matlab,Auto CAD, Microsoft Excel, Word, Powerpoint, Verilog DHL(in processing). - 2017 Oct 23
Embedded System Engineer
San Jose, CA
... Skills VHDL, Verilog and System Verilog experience. FPGA/Digital Logic Design experience. C, C++, Embedded C and OOP trained. MATLAB and Simulink trained. JAVA Programmer. Possess good understanding of I2C, SPI, DDR and UART protocols. Can Design ... - 2017 Oct 12
... Skills VHDL, Verilog and System Verilog experience. FPGA/Digital Logic Design experience. C, C++, Embedded C and OOP trained. MATLAB and Simulink trained. JAVA Programmer. Possess good understanding of I2C, SPI, DDR and UART protocols. Can Design ... - 2017 Oct 12