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Post Silicon Validation

San Jose, California, United States
November 29, 2017

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Fernando Iriondo

San Jose, CA

Phone: 408-***-****



Over 15 years of experience in Software/Hardware positions working for companies such as Intel and Broadcom. My main area of expertise is in CPU and SoC Chip Validation/Verification.


University of California San Diego

Major: Electrical Engineering, BS.

Area of Focus: Computer Design.

Date of Graduation: September 1996.


Software Developer, Self-Employed.

Bilbao Area, Spain

March 2016 – Present,

After taking a year sabbatical, I started working on a finance software app for traders.

Senior Staff IC-Design Engineer (Post Silicon Validation), Broadcom.

Santa Clara, CA.

May 2011 – June 2015.

I was actively involved in the validation of multicore/multithread MIPS processors from Netlogic/Broadcom.

I, successfully, developed and maintained several core validation tests for CPUs that increased yields.

oI integrated different individual unit level tests such as Core, NET, USB, PCI, I2C, etc into one main test so that production could scan out parts during manufacturing.

I was able to successfully increase yields by integrating as many unit level tests as possible, and using parallelism, to reduce total execution time while maintaining coverage.

Also, I developed Power Tests that were used to measure CPUs max power.

oI was able to successfully attain maximum power consumption from each component.

Thanks to my efforts the company was able to increase yields and measure accurately CPU max power consumption.

The main technologies used were C, Perl, JTAG debugger, xloader, and U-Boot.

Software Design Engineer, ZIV (R&D Dept)

Bilbao Area, Spain.

October 2007 – July 2010

I worked on embedded system development and application software development.

I assisted in the development of a Linux based Embedded System that was written in C++.

Among several of my accomplishments these were the following:

o I implemented several services like a small FTP server which helped customers maintain the system manageable and helped transfer data quickly.

oI modified the NTP server service so that the system, which was using 3G technology, could save money.

oI integrated software that communicated with the embedded system through the serial interface using XMODEM /YMODEM protocols that enabled clients to transfer data into the embedded system.

I also assisted in the development and maintenance of a Windows based application, written in FoxPro, which was used to configure digital control and protection systems for electrical substations.

oI had to get up to speed rather fast with FoxPro (never used before), so that I could start adding functionality to the software.

oI implemented several new Scada protocols to the substations.

oI also helped the rest of the programmers to help improve the existing code.

Verification Engineer, Intel Massachusetts Inc.

Boston Area, MA.

October 2004 – April 2007

Contributed to Intel’s QuickPath (formerly known as CSI - Common System Interface) physical layer Co-Sim verification effort.

oSuccessfully developed a test generation tool, written in Perl, which greatly helped the generation of the different tests used on the simulations.

oActively worked on test generation, regression, and debug for the various CPU-Repeater-Mem topologies.

Initially I helped the T-Box team in the validation of the CPU JTAG Master Controller (T-Box)

oWrote a C++ reference model of JTAG Master Controller which was successfully used as a model checker.

oActively participated in the JMC verification cycle, by generating random constraint based tests, running regressions, and debugging the regression results.

Sr. Verification Engineer, Sonics Inc.

Mountain View, CA.

March 2001 – July 2003

As an independent contractor I participated in the functional verification effort for a Texas Instruments’ SoC chip composed of over 20 initiator/target cores and incorporated Sonics’ OCP technology.

oI successfully completed the test environment OCP data model, in C++, that was used for random constraint base test generation.

oPerformed code overage using SureCov.

oIn addition to the mentioned tasks I ran regressions and performed daily debug on the results.

oUsed TestBuilder for test bench development

As an employee I worked on additional functional verification projects: A Memory Scheduler called MemMax, an OCP Merger, and an Error Recovery feature of Sonics’ Silicon Backplane Smart Interconnect.

For the Memory Scheduler I successfully developed the test plan and performed all necessary RTL functional verification.

oI successfully developed, using Perl, all the tests described in the test plan.

oThe tests were a combination of directed and random tests as were described on the test plan.

oI worked on the regression environment; running tests nightly and debugging daily issues.

For the OCP Merger (Multiple single threaded OCP masters to a multithreaded OCP Interface), I developed a test plan, generated all the necessary tests and ran nightly regressions.

For the Error Recovery Feature of the main Sonics product we injected constraint based errors in the already random based existing tests and checked that the component recovered correctly.

Verification Engineer, Intel Corporation.

Santa Clara, CA

July 1997 – July 1999.

System Level Validation (SLS) on 440-MX (low power mini notebook chipset).

oActively involved in writing a system level test plan that included back-to-back traffic and multi-master traffic.

oUsed Perl to write the ATG (Automatic Test Generator) that was used to generate the B2B and multi-master tests from the test plan.

oRan and debugged regression results.

Component Level Validation (CLS) and System Validation (SV) on a floppy disk controller (FDC) part of a Super-IO chipset.

oDuring the component level verification of the floppy disk controller I worked with Perl to generate the different tests.

oI ran regressions and compared the results to golden files that were previous visually verified for correctness.

oDuring the system validation I worked with Assembly Language programming to generate tests. The FDC was mapped into a FPGA and we I used those assembly language written tests to validate it.

Hardware Engineer, Romer Incorporated

Carlsbad, CA

March 1997 - July 1997.

Testing and validation of PCBs.

Assembly Language programming.

Computer Operator/Programmer, University of California

San Diego, CA.

May 1994 - June 1996.

Installation and maintenance of computer systems.

Assist with departmental tasks and maintenance of data code tables on the IBM mainframe.


Programming: C/C++, Perl, Verilog, Assembly, VHDL.

Technologies: OCP, Intel X86, MIPS.


Available upon request.

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