| Resume alert | Resumes 21 - 30 of 142 |
Engineer Network
Dallas, TX
... Implemented & verified the design using both Verilog and VHDL in Quartus II Software. Vending Machine Using FSM Designed a Finite State Machine for Vending Machine functionality, implemented the state machine using a VHDL program and tested the ... - 2020 Sep 07
... Implemented & verified the design using both Verilog and VHDL in Quartus II Software. Vending Machine Using FSM Designed a Finite State Machine for Vending Machine functionality, implemented the state machine using a VHDL program and tested the ... - 2020 Sep 07
Junior Standing in Electrical Engineering
Dallas, TX
... Office, Java, C Assembly, Matlab, Verilog, LabVIEW Teamwork, Solving Problems, Time Management, Fluent in English and Vietnamese RESEARCH PROJECT: Research Assistant, Southern Methodist University, Dallas, TX Fall 2019 - Assisted PhD candidate Ms. ... - 2020 Aug 18
... Office, Java, C Assembly, Matlab, Verilog, LabVIEW Teamwork, Solving Problems, Time Management, Fluent in English and Vietnamese RESEARCH PROJECT: Research Assistant, Southern Methodist University, Dallas, TX Fall 2019 - Assisted PhD candidate Ms. ... - 2020 Aug 18
Engineer Python
Richardson, TX
... 2018 Pune, India TECHNICAL SKILLS Programming languages C (data structures), Python, Embedded C, MATLAB, Assembly Language, Verilog HDL, SystemVerilog, SQL Technologies CUDA knowledge,Machine Learning (Classification, Regression, Clustering), Deep ... - 2020 Jul 29
... 2018 Pune, India TECHNICAL SKILLS Programming languages C (data structures), Python, Embedded C, MATLAB, Assembly Language, Verilog HDL, SystemVerilog, SQL Technologies CUDA knowledge,Machine Learning (Classification, Regression, Clustering), Deep ... - 2020 Jul 29
Engineer Design
Plano, TX
... This involved the design of those test structures needed to isolate various aspects of the modeling environment ranging from the functionality of the verilog and circuit models to the spice process models and parasitic extraction decks. There were ... - 2020 May 02
... This involved the design of those test structures needed to isolate various aspects of the modeling environment ranging from the functionality of the verilog and circuit models to the spice process models and parasitic extraction decks. There were ... - 2020 May 02
Engineering, MATLAB, C PROGRAMMING, Python
Richardson, TX
... Software Packages: MATLAB, Cadence, Verilog, VHDL, PSpice, Xilinx, MS Office. Operating systems: Windows, Linux Ubuntu. Networking Protocols: TCP/IP, UDP, ARP, RIP, OSPF, BGP, MPLS, DNS, NAT, DHCP, HTTP, VoIP, CSMA. Networking Software/Tools: ... - 2020 Feb 27
... Software Packages: MATLAB, Cadence, Verilog, VHDL, PSpice, Xilinx, MS Office. Operating systems: Windows, Linux Ubuntu. Networking Protocols: TCP/IP, UDP, ARP, RIP, OSPF, BGP, MPLS, DNS, NAT, DHCP, HTTP, VoIP, CSMA. Networking Software/Tools: ... - 2020 Feb 27
Customer Service Manager
Dallas, TX
... Indian Space Research organization May 2013 - July 2013 Embedded System Intern (WinDriver, Verilog ) Bangalore, IN Reviewed product requirements and logic diagrams to develop high performance, cross platform USB device drivers and custom hardware ... - 2019 May 20
... Indian Space Research organization May 2013 - July 2013 Embedded System Intern (WinDriver, Verilog ) Bangalore, IN Reviewed product requirements and logic diagrams to develop high performance, cross platform USB device drivers and custom hardware ... - 2019 May 20
Engineer Software
Plano, TX
... Mahereen Sultana Tazree Plano, TX, USA 512-***-**** (cell) ac8l98@r.postjobfree.com Programming Language Java, OOP in C#, C/C++, Python, Unix Shell scripts like bash, Assembly, Language, Verilog, HSPICE Database Software Tools SQL, Oracle Software ... - 2019 Feb 26
... Mahereen Sultana Tazree Plano, TX, USA 512-***-**** (cell) ac8l98@r.postjobfree.com Programming Language Java, OOP in C#, C/C++, Python, Unix Shell scripts like bash, Assembly, Language, Verilog, HSPICE Database Software Tools SQL, Oracle Software ... - 2019 Feb 26
Python, C, Matlab, AMPL, Multisim, Jupyter, Github, Kaggle,Java,Visual
Dallas, TX
... to divide data samples Skills Programming Languages/Tools: Python, C, Matlab, AMPL, Multisim, Jupyter, Github, Kaggle,Java,Visual Basic,Verilog,Quartus. Speaking Languages: Fluent in English and Mandarin (able to read traditional characters). - 2019 Feb 12
... to divide data samples Skills Programming Languages/Tools: Python, C, Matlab, AMPL, Multisim, Jupyter, Github, Kaggle,Java,Visual Basic,Verilog,Quartus. Speaking Languages: Fluent in English and Mandarin (able to read traditional characters). - 2019 Feb 12
Engineer Electrical
Dallas, TX
... Electrical Engineering GPA: 3.70 University of Mumbai, Mumbai, India Graduation Date: May 2014 Master of Sciences Electrical Engineering GPA: 3.05 Technical Skills: Programming Languages: C/C++, Java, Python, MATLAB, Verilog HDL and Assembly. ... - 2019 Feb 06
... Electrical Engineering GPA: 3.70 University of Mumbai, Mumbai, India Graduation Date: May 2014 Master of Sciences Electrical Engineering GPA: 3.05 Technical Skills: Programming Languages: C/C++, Java, Python, MATLAB, Verilog HDL and Assembly. ... - 2019 Feb 06
Fresh Graduate/Entry Level Software Developer
Dallas, TX
... metadata SFTPs to web service which renders a model in Blender to display on web Arithmetic Logic Unit (Digital Logic) Verilog Lead team by delegating roles and assignments Implemented an ALU using Verilog with functions for addition, subtraction ... - 2018 Nov 01
... metadata SFTPs to web service which renders a model in Blender to display on web Arithmetic Logic Unit (Digital Logic) Verilog Lead team by delegating roles and assignments Implemented an ALU using Verilog with functions for addition, subtraction ... - 2018 Nov 01