Engineer Design

Aubrey Q. Neve

**** *** ****** **. *** #**** Phone: Cell 512-***-****

Plano, TX. 75075 **********@*****.***

Objectives:

Senior Design Engineer / Engineering Management

Summary:

A well rounded back ground in all aspects of complex ASIC/MCU, and FPGA design projects, from product specification through production test and qualification. A solid background in EDA tools (IC/PCB) for analog and digital circuit/layout design, RTL functional verification, and logic synthesis, timing closer, and SoC integration, floor planning and place and route. A skilled software developer experienced programming in C/C++, Assembler, CShell, Perl, Cadence Skill, and TCL. A back ground working with in an RTOS environment. Hands on experience design/debug of multiple serial communication protocols I2C, SPI, CAN, UART, USB and Ethernet. Solider back ground in project and or engineering management. Experience:

7/2015 to 5/2020 Aragio Solutions Senior Engineer (Manager Test Lab) My primary responsibility was post silicon verification of all Aragio IP 40nm through 12nm. This ranged from ESD to Latch Up test, as well as full functional test and pull parametric test across all PVTs. I further generated the finale report quilfiing the designs with both Global Foundries and TSMC.

8/2014 to 10/2014 Celerint (Contract) Senior Engineer Embedded systems design, Tandem Handler Test Cell, Software/firmware development and system integration. System level cost reduction. Migrated system architecture from LabView/PXI to a dedicated controller built on PC-104 embedded system.

3/2014 to 8/2014 Allied Fence & Security (Contract) System Engineer Sales and Support My responsibility ranged from sight survey, system design, BOM development, through the installation of CCD surveillance systems.

6/2011 to 11/2013 Stryker Instruments Senior Staff Product Engineer Electrical I served as R&Ds division level subject matter expert for the Neptune Waste Management System as well as the SmartPump Tourniquet System.

My responsibility covered all aspects of the products life cycle from design through all staining engineering activity. These duties ranged from the developed system specification, through circuit and PCB layout design and failure/effect hazard analysis, to embedded software (C++) development. Primary responsibilities covered the verification/validation of system level specifications, manufacturing processing QA validation and test development, LabView, as well as UL, IEC, CSA, and FDA regulatory compliance.

Supported Embedded controllers

Rover/Docker Main Rover uEDMS: Atmel AT91SAM7 (ARM 7) proprietary RTOS Rover subsystems Slaves:

Vacuum, Smoke Blower, IV pole

Rover/Docker Power Coupler: Microchip dsPIC33 proprietary RTOS Volume Measurement: XILINX FPGA

Docker EDMS: Atmel AT91SAM9 (ARM 9) Windows CE 5

SmartPump Tourniquet System: Atmel AT89LP (8051) proprietary RTOS CAD/EDA tools:

Cadence OrCAD/Allegro PCB Design Suites

Mentor Graphics PADS

Windows Platform Builder

Green Hills

Atmel Studio

Perforce

LabView

5/2009 to 3/2010 Oehler Research (Contract) Project Lead Ballistic Instrumentation Developed system specification, circuit and PCB layout design (Signal Conditioning and MPU interface logic), and developed the embedded software (C++) for Oehler Research’s System 85 Ballistic Instrumentation System and Model 36 Chronograph. Work with and had over sight authority of one subcontractor developing the systems graphical users interface. Sensor IP: Chamber/bore pressures Piezoelectric transducer or a strain gauge Muzzle Velocities Infrared photo detection

Down Range Piezoelectric acoustic microphones

System IP: Embedded controller Freescale MCF5213

USB Serial FTDI FT232R

Embedded GPS NavSync CW25

Embedded RF Digi XBee-Pro

1/1992 to 1/2009 Freescale Semiconductor (Motorola SPS) 1999 to 2009 Senior Engineering Specialist / Project Lead I/O Design In this position I supported the development of the IP (Intellectual Property), 330nm through 65nm, and the I/O circuitry supporting the Imaging Systems, Industrial Control, and Automotive and Transportation Groups. Directed and advised five analog circuit designers and two layout designer on the circuit’s implementations impact to system integration.

Generated and supported of all physical and functional models comprising a complete Digital Design Kit (DDK) and Physical Design Kit (PDK).

Oversaw the verification of models and IP modules, managed the configuration management (CM), and distribution of the Design Library.

CAD support of the EDA tools and development of a seamless design flow integrating IP into SoC Migrated from a Synopsis centric design flow to fully Integrated Cadence design flow. Supported IP:

* GPIO (General Purposes I/O) Programmable Drive/Slew Rates,

* PCI, USB, LVDS (Low-Voltage Differential Signaling) Buses

* SDR/DDR Memory Interface

* PLL’s

* Clock Tree balancing circuit

* Low Power management circuitry

* PWM-Delay (Proprietary IP for Hewlett Packard)

EDA tools and environment supported:

* Platforms: Solaris, RedHat

* Revision Control Release and Distribution: CVS,

Synchronicity DesignSync/ProjectSync, ClearCase

* Circuit/Layout design: Mentor Graphics, Cadence Virtuoso

* Circuit Simulation: Hspice, Freescale MICA, Spectra

* Library Characterization: Silicon Metrics, Freescale Karma

* Logic Synthesis, Signal Integrity,

Low Power Management, Timing Closer: Cadence and/or Synopsis Design Flow EDA tools

* Functional Verification: ModelSim VHDL

* DFT: Mentor Graphics FastScan

* DRC and LVS: Caliber

* Parasitic Resistance and

Capacitance extraction: StarRC

1997 to 1999 Senior Engineer / Process and Design Library Qualification In this position I supported the development, qualification and distribution of the Standard cell and I/O DDK design libraries. I was primarily responsible for the characterization and timing/power modeling of the CDR2 320nm Standard Cells Further responsibilities included the qualification of the process and the standard cell design library. This involved the design of those test structures needed to isolate various aspects of the modeling environment ranging from the functionality of the verilog and circuit models to the spice process models and parasitic extraction decks. There were also test structures designed to verify the back end timing closer of our ASIC design flow. I was also responsible for the design and build of the test chip as well as the development of the test program (Teradyne J971).

I also correlated and issued the final report on the simulated vs. measured results qualifying the library as well as our ASIC design flow to a six sigma process flow.

1994 to 1997 Senior Electrical Failure Analyst /Manager Test and Fault Isolation Purposed developed and implemented a plan to replace the use of an applications development PCB boards to provide the stimulus need to isolate a failures to one centered on the use of a low cost turn-key digital test system. Managed a group of one hardware systems engineer and one software developer as well as two engineering technicians. I was responsible for all aspects of this program. This ranged from tester selection through the design of the interface to the micro-probe station to the software development (C) of the ATPG (Automated Test Program Generation) software This program was fully implement in the High End Failure Analyses Lab as well as the Low End/Mid-Range Failure Lab with an install base of fifteen systems and was under investigation by one of Motorola’s offshore design centers. I work with the following test systems and ATPG software.

* Teradyne J750 J971/973

* HiLevel ETSXXX

* Custom HP VXI test System

* LabView

* TSSI TDS

* Agilent (HP) 3070

1992 to 1994 Electrical Failure Analyst

In this position I supported the 68000 through the 68040 as well as the 683XX embedded processor product lines. Responsibilities were to isolate the failing element de-process the die and identify the root cause of the failure. Then report back the FAB, product groups or customers as to the effect on yields and or quality. 2/1990 to 1/1992 Compaq Computer / Technical Writer While in this position I developed the following training programs:

* Assemble Language Programming and Debug of New Products Using the Power on Self-Test Routine (POST).

* PC System Architecture, Compaq model 486/50L

* Introduction to RISC Architecture

* Assemble Language Programming MIPS R4000

I authored the following papers.

* White papers covering new products

* White paper RISC vs. CISC Architecture

* White paper Comparing/Contrasting various Cache Architectures 2/1985 to 1/1990 General Dynamics / Senior Design Engineer Systems integration, SRU/LRU functional test and verification F-16, F-111, A-12. These duties ranged from circuit design and PCB layout design and software development to the forecasting of scheduling and manpower from the start of the program through its deployment in the Electronic Manufacturing Center.

I have hands on experience with ATE and production test development covering MIL-1553 bus, ADC, DAC and DC/DC converters, RF.

1/1984 to 12/1985 Alvin Community College / Instructor Developed and taught accredited courses for the Computer Science department. Education:

1985 University Of Houston / Bachelor of Science in Electronics 1982 Alvin Community College / Associate in Applied Science in Electronics

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