| Resume alert | Resumes 41 - 50 of 191 |
Assistant Design
North Hills, CA
... LSI_10k Library – Verilog CSUN February 2019 – March 2019 • Created individual cells that were individually tested to function at the specified timings. • Determined nominal delay using Synopsis Design Compiler to derive timing reports examining all ... - 2019 Mar 30
... LSI_10k Library – Verilog CSUN February 2019 – March 2019 • Created individual cells that were individually tested to function at the specified timings. • Determined nominal delay using Synopsis Design Compiler to derive timing reports examining all ... - 2019 Mar 30
Electrical Engineer
Los Angeles, CA
... • Software: C/C++, MATLAB, Python, Machine Learning (TensorFlow), Arduino, x86-Assembly, Verilog PROFESSIONAL EXPERIENCE ARNI UCLA Research Laboratory Los Angeles, CA Research Intern, Information Theory June 2018 – August 2018 Researched Machine ... - 2019 Mar 04
... • Software: C/C++, MATLAB, Python, Machine Learning (TensorFlow), Arduino, x86-Assembly, Verilog PROFESSIONAL EXPERIENCE ARNI UCLA Research Laboratory Los Angeles, CA Research Intern, Information Theory June 2018 – August 2018 Researched Machine ... - 2019 Mar 04
Electrical Engineer Computer Engineering
Los Angeles, CA
... a private server ●Web-based spectral analysis and visualization of vibrational data TECHNICAL / NON-TECHNICAL SKILLS: ●MATLAB, PSpice, CadSoft EAGLE, IAR Embedded Workbench, Verilog, vPython, C Programming Language, LC-3 language, Microsoft Office - 2019 Feb 03
... a private server ●Web-based spectral analysis and visualization of vibrational data TECHNICAL / NON-TECHNICAL SKILLS: ●MATLAB, PSpice, CadSoft EAGLE, IAR Embedded Workbench, Verilog, vPython, C Programming Language, LC-3 language, Microsoft Office - 2019 Feb 03
Design Engineer,Embedded System, VLSI, Verification, Test, C, C++
Los Angeles, CA
... (Tomasulo), Multicore (CMP), VLIW, Superscalar, SMT(HTT), Vector Processors Verification: UVM, Formal Verification, System Verilog Assertion Test Knowledge: DFT, Boundary Scan, ATPG, Fault Simulation Data Transmission Protocols: Cache Coherency ... - 2019 Jan 25
... (Tomasulo), Multicore (CMP), VLIW, Superscalar, SMT(HTT), Vector Processors Verification: UVM, Formal Verification, System Verilog Assertion Test Knowledge: DFT, Boundary Scan, ATPG, Fault Simulation Data Transmission Protocols: Cache Coherency ... - 2019 Jan 25
Computer Engineering System
Los Angeles, CA
... SKILLS: Programming Languages: C++, C, Java Hardware Description Languages: System Verilog, Verilog, System C Scripting Languages: Python, Bash, Perl Verification Methodologies: UVM, FPGA Prototyping, Formal Verification, UPF PROJECTS: Coverage ... - 2019 Jan 23
... SKILLS: Programming Languages: C++, C, Java Hardware Description Languages: System Verilog, Verilog, System C Scripting Languages: Python, Bash, Perl Verification Methodologies: UVM, FPGA Prototyping, Formal Verification, UPF PROJECTS: Coverage ... - 2019 Jan 23
Hardware Engineer
Fullerton, CA
... 4-bit Microprocessor Design in Verilog • Developed Verilog program for given instruction set from the control circuit. Created constraint file and clock as per given specification. - 2019 Jan 21
... 4-bit Microprocessor Design in Verilog • Developed Verilog program for given instruction set from the control circuit. Created constraint file and clock as per given specification. - 2019 Jan 21
Data Entry
Carson, CA
... in the following programs/languages: Microsoft Word Microsoft Excel SQL Server 2012 Tableau Axure Google Map Engine VHDL Verilog C C++ Python MIPS Matlab Simulink Education BS in Computer Engineering California State University Bakersfield, ... - 2018 Dec 27
... in the following programs/languages: Microsoft Word Microsoft Excel SQL Server 2012 Tableau Axure Google Map Engine VHDL Verilog C C++ Python MIPS Matlab Simulink Education BS in Computer Engineering California State University Bakersfield, ... - 2018 Dec 27
Software Engineer
Los Angeles, CA
... PROGRAMMING SKILLS PROGRAMMING LANGUAGES C/C++ Python MySQL Schell Script Java Ocaml MongoDB PHP Lisp JavaScript HTML/CSS Verilog RELATIVE PLATFORMS & ENVIRONMENTS Docker Nodejs Angular Git Linux OSX PROJECTS Random Number Generator Summer 2018 ... - 2018 Dec 17
... PROGRAMMING SKILLS PROGRAMMING LANGUAGES C/C++ Python MySQL Schell Script Java Ocaml MongoDB PHP Lisp JavaScript HTML/CSS Verilog RELATIVE PLATFORMS & ENVIRONMENTS Docker Nodejs Angular Git Linux OSX PROJECTS Random Number Generator Summer 2018 ... - 2018 Dec 17
Engineer Computer Engineering
Compton, CA
... Systems TCPIP Python 3.6 Course Projects Designed and implemented a traffic light controller using a FPGA board in Verilog Designed and implemented a digital clock in Verilog Hands on experience with standard electronics lab equipment, FPGAs, ... - 2018 Nov 15
... Systems TCPIP Python 3.6 Course Projects Designed and implemented a traffic light controller using a FPGA board in Verilog Designed and implemented a digital clock in Verilog Hands on experience with standard electronics lab equipment, FPGAs, ... - 2018 Nov 15
Electrical Engineering Design
Los Angeles, CA
... SKILLS Verilog, System Verilog, UVM, C, C++, Python Platforms Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs. PROJECTS Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular ... - 2018 Oct 30
... SKILLS Verilog, System Verilog, UVM, C, C++, Python Platforms Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs. PROJECTS Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular ... - 2018 Oct 30