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Electrical Engineering Design

Location:
Los Angeles, California, United States
Posted:
October 30, 2018

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Resume:

Yuntao SONG

ac7jq7@r.postjobfree.com 626-***-****

EDUCATION

Aug 2017 - May 2019 UNIVERSITY OF SOUTHERN CALIFORNIA

-Electrical Engineering, Master of Science GPA 3.38(3.92 excluding 1st semester)

-Courses: EE580(System Verification), 577AB(VLSI System Design), 658(DFT), 599(soft- ware for ee), 457(Computer System Organization), 477(MOS VLSI Circuit Design) Sep 2013 - Jun 2017 CHINA AGRICULTURAL UNIVERSITY

-Electronic Information Engineering, Bachelor of Engineering

-Graduation with honor: Outstanding Graduates Cadres in Beijing PROFESSIONAL EXPERIENCE

Top2 team of Full-Custom Pipline CPU design

Led the five stage pipelining CPU which IF and part of ID stage were required in python and others were in full-custom design.

Designed schematic and changed traditional five stage CPU to four stage. The Mem- ory part I designed by working with EX stage simultaneously so some control signals will not be passed in other stages(In project, address offset will not be considered) . I completed major part of layout except for multiplier in ALU and its connection. I experienced how to minimize area, accelerate circuits and manage layout. Cognitive Computing in Hardware - Approximate Multiplier

Developed an approximate multiplier based on IEEE754 for saving power, area and delay.The machine learning engine KNN algorithm was used to decrease fraction part under constraint of affordable error rate. I supported the idea and helped verify and simulate approximate multiplier on Vivado. Collect data for machine learning engine. The approximate multiplier was implemented and compared with full bit multiplier on Image Processing and Neural Networks.

SKILLS

Verilog, System Verilog, UVM, C, C++, Python

Platforms

Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs.

PROJECTS

Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular Expres- sion, Regression, Machine Learning(KNN, K-means, SVM), SAT solver, SQL.

UVM: Performed Multi-cores and FIFOs. For multi-cores, I regard the processors as prototypes and verify communication between routers and interfaces.

System Verilog: Managed a company system which includes names, work types, in- formation of employers and employees. I verified it by OOP.

FPGAs: Developed Traffic lights, Vending Machine, An algorithms for encryption communication.



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