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Assistant Design

North Hills, California, United States
March 30, 2019

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Jeremy Perez 818-***-****


Bachelor of Science in Computer Engineering Expected Graduation: May 2019 California State University Northridge (CSUN)

Cumulative GPA: 3.12/4.00


Beamforming Antenna - MATLAB CSUN August 2018 - Present

• Designed an omnidirectional antenna that operates between 1.75-2.12GHz with the ability to steer nulls. The radiation pattern was controlled by converting the signal to digital then using a microcontroller.

• Performed theoretical studies of tradeoffs between number and types of antennas and how they affected the beam steering.

• Processed digital signals using a software defined radio to record our analog antenna input signals.

• Created algorithms that determined the strongest angle of arrival and steered the beam to that direction.

• Developed MATLAB code that implemented those algorithms and displayed theoretical results. Pac-Man Game - FPGA CSUN March 2019 – Present

• Designed a Pac-Man-esque game using Xilinx Zynq SoC PS2, VGA, and SRAM.

• Created detail design sprites for the character, objects, and score using VHDL.

• Implemented the play area using a control array to represent the location of sprites

• Programmed a chasing algorithm for the ghost.

LSI_10k Library – Verilog CSUN February 2019 – March 2019

• Created individual cells that were individually tested to function at the specified timings.

• Determined nominal delay using Synopsis Design Compiler to derive timing reports examining all possible paths and obtaining accurate cells.

Project Management System – C# CSUN August 2018 – December 2018

• Determined an estimate for the overall effort required and duration to complete the project.

• Created a request of proposal by estimating cost, scheduling, and creating storyboards of requirements.

• Designed high-level design, GUI prototypes, and detailed designs using agile methodologies.

• Implemented our design to develop classes, methods, and tables into a functional project management system.

RISC-Y Processor – System Verilog CSUN January 2018- May 2018

• Modeled smaller components that would be implemented into the RISC-Y processor which included an 8-bit register, scalable MUX, scalable register files, 8-bit ALU, and sequence controller.

• Implemented modules to create a RISC-Y processor which could function as a microcontroller.

• Tested the processor by programming it to perform a series of tasks: fetching instructions, decoding instructions, performing ALU operations, storing results, and repeating. WORK EXPERIENCE

Fundamentals of Electrical Engineering Lab Assistant CSUN January 2019- Present

• Assisted the instructor with the responsibilities of ensuring all students were actively engaged in experimental procedures and understood critical concepts.

• Presented software tutorials to introduce students to simulation SKILLS

Software: Microsoft Office, PSpice, Keil μVision, Quartus Prime, Simulink, Synopsys VCS, Xilinx Vivado Programming & HDL: Java, Matlab, ARM Assembly, System Verilog, VHDL, C, C# Technical: Circuit Assembly, Oscilloscope, Digital Multimeter, Spectrum Analyzer, Digital Design, FPGA programming, Hardware verification, RTL coding, test bench development

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