AMOGH AVINASH

Address: **** ******** ******, *** ***, Los Angeles, CA-90007 Email: ac792f@r.postjobfree.com Cellphone: +1-213-***-**** LinkedIn: https://www.linkedin.com/in/amoghavinash EDUCATION:

University of Southern California, Los Angeles May 2019 Master of Science, Computer Engineering

Related Coursework: System Verification, Software Design and Optimization, Computer System Operations, Computer Architecture for IoT Enablers, Internet and Cloud Computing, Design for Test. PES Institute of Technology, Bangalore May 2017

Bachelor of Engineering, Electronics and Computer Engineering Related Coursework: Low Power VLSI Design, Advanced Digital Design, Real-Time Operating Systems. SKILLS:

Programming Languages: C++, C, Java Hardware Description Languages: System Verilog, Verilog, System C Scripting Languages: Python, Bash, Perl Verification Methodologies: UVM, FPGA Prototyping, Formal Verification, UPF PROJECTS:

Coverage Driven Verification of AXI-Protocol Using UVM (System Verilog, UVM, Questa-Sim) October 2018

• Verified the processor and memory interface through AXI channels using UVM, achieving a coverage of 81.2 %.

• Assertions conforming to the AXI protocol were implemented and the interconnect routing protocol was verified. Verification of a Round-Robin Arbiter and their connected FIFO’s using UVM (System Verilog, UVM, Questa-Sim) Sep 2018

• Verified the working of a round robin arbiter interconnected to 4 FIFO’s using UVM, achieving a coverage of 72%.

• Assertions for signals relating to the working of the FIFO such as full and empty were implemented. 5-stage Linear Pipelined CPU (System Verilog, Verilog, Questa-Sim) July 2018

• Implemented a basic 5-stage with IF stage, ID stage, EX-1, EX-2 and WB stage for basic arithmetic functions.

• Appropriate Forwarding Unit(FU) and Hazard Detection Unit(HDU) were used to handle data dependencies.

• A System Verilog testbench was implemented to exhaustively test the Design under test(DUT). Verification of a multi-core processor using System Verilog (System Verilog, Questa-Sim) June 2018

• Verified the functioning of the dispatcher to a 4-core processor using System Verilog testbenches and assertions.

• Implemented cover-groups relating to the instruction type and the output of the writeback stage was verified. Verification of an Asynchronous FIFO using System Verilog (System Verilog, Verilog, Questa-Sim) June 2018

• Implemented driver, interface and scoreboard in System Verilog to verify the working of an asynchronous FIFO. FPGA verification using Altera DE2 (Verilog, Quartus Prime) June 2018

• Implemented and verified the working of a 4x4 Baugh-Wooley multiplier and Traffic light controller using Altera DE2.

• Designed and verified the working of a multicore 5-stage MIPS pipelined processor using Altera DE2. Machine learning (Python, Unsupervised learning, Reinforcement learning, Scikit-learn, Linux) May 2018

• Implemented k-means algorithm and SVM using LIBSVM’s kernel SVM.

• Implemented value iteration for the Frozen-Lake environment using Open-AI Gym. Self-Optimizing Network on Chip (System C, Network on Chip Simulator) April 2018

• Developed an algorithm to route various flits on a NoC by dynamically choosing between two frequencies.

• The frequencies were chosen depending on the channel fitness of the buffer. Stochastic Geometry for Pattern Recognition in City Mapping (C++, Python, Open-CV) April 2018

• Implemented Open CV for C++ and Python to extract coordinates of curves in a city map using Hough transform.

• Stochastic geometry and k-means clustering was used to obtain the similarity score between two cities. Out of Order Execution Divider (Verilog, Model-Sim) September 2017

• Four parallel dividers were designed to demonstrate In-order Issue, Out of order Execution and In-order Completion.

• Implemented Dispatch unit, Issue unit and a Re-order Buffer(RoB) to ensure in order completion. WORK EXPERIENCE

AERX Labs, Intern June - August 2016

• Worked on a team which aimed to implement speech recognition on a patented flight simulator.

• Wrote Python scripts to automate the Speech-to-text and the Text-to-speech process.

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