YASHWIN REDDY KODURU

Los Angeles, California

https://www.linkedin.com/in/yashwin-reddy-koduru/

ac6az5@r.postjobfree.com 213-***-****

EDUCATION

University of Southern California, Los Angeles, U.S.A August 2016 – May 2018 Masters of Science, Electrical Engineering (VLSI Design and Computer Architecture) GPA : 3.53/4.00 Coursework: •EE 457: Computer Systems Organization •EE 477: MOS VLSI Circuit Design •EE 557: Computer Systems Architecture

•EE 577A/B: VLSI System Design I/II •EE 560: Digital System Design •EE 658: Diagnosis and Design of Reliable Digital Systems

Chaitanya Bharathi Institute of Technology (Osmania University), Hyderabad, India August 2012 - June 2016 Bachelors of Engineering, Electronics and Communications Engineering GPA : 4.00/4.00 SUMMARY OF SKILLS

Programming in C, C++, Assembly Behavioral Simulation using Modelsim/SimVision

Design automation/scripting with Python, Perl, Tcl Logical Equivalence using Cadence Confromal

Behavioral simulation using SPECTRE, HSPICE Design Synthesis using Synopsys Design Compiler

Signal processing and simulation on MATLAB

Front-end RTL design using Verilog HDL/VHDL

Static Timing Analysis with Synopsys Primetime

Place and Route using Cadence Encounter (EDI)

Functional Verification using SystemVerilog/Verilog Verification using UVM, OVM, UPF Methodologies

On-board testing with Chipscope, UART on Xilinx ISE Layout, Schematic Design using Cadence Virtuoso WORK-EXPERIENCE

University of Southern California, Graduate Research Assistant August 2017 – April 2018

Project focused on an optimized framework for load balancing for exascale multicore systems represented as dynamic application directed graph.

Responsible for design of the profiler, which analyses the critical areas of program for performance tweaking, increasing the throughput by at least 20%. Technology Aspirations, Network Engineering Intern July 2014 – August 2014

Engaged in LINUX based networking in the development of Value-Added-Services(VAS) for customers in remote countries.

Responsible for remote server cross referencing and monitoring with the assistance of NAGIOS. ACADEMIC PROJECTS

Design and Implementation of ATPG and Fault Simulator for Combinational Circuits October 2017 – December 2017

Working as a team of four to develop a pre-processor, two ATPG algorithms (D algorithm, PODEM) and two fault simulators (Parallel Fault Simulation, Deductive Fault Simulation) for combinational digital circuits, applying them to ISACS benchmark circuits to get maximum fault coverage. Design and Implementation of DDR3 Memory Controller based on Denali’s Model October 2017 – December 2017

Semi-custom ASIC design of DDR3 SDRAM Controller implementing scalar, block and atomic read/write features in Verilog. The design flow includes RTL design, synthesis and automated placement & routing, achieved using Synopsys DC, and Cadence Primetime, Encounter for STA and PAR. Implementation of Out-of-Order Execution Tomasulo CPU May 2017 – July 2017

Designed a Copy-Free Check pointing (CFC) unit to restore the F-RAT (Front-end Register Alias Table) in case of a branch misprediction, an Issue unit (IU), a 2-stage Dispatch unit, and a Re-Order Buffer (ROB). Integrated the overall system and implemented it on Xilinx Artix-7 FPGA board. Full Custom Design of General Purpose 16-bit CPU February 2017 – April 2017

Designed a fully custom 32-bit 5 stage pipelined RISC processor with a 512bit SRAM in Cadence Virtuoso - Schematic and Layout. Simulations done using Spectre and verification using backend Python Scripting. Front-end scripting for vector file creation based on the instruction stream. Microarchitecture Enhancement to Baseline Processor March 2017 – April 2017

Modified existing base processor by changing cache latencies, branch prediction model, machine width and computational resources. CACTI and estimator tools provided latencies and area/transistors used. Four benchmarks were used and the improvement went from 600 to 4168 MIPS. Implementation of HDMI Interface on Spartan-6 FPGA Board January 2016 – March 2016

Designed a HDMI based TMDS encoder and serializer in Xilinx ISE Design Suite using Verilog HDL. Implemented on Spartan-6 FPGA board to display a random pattern onto a LCD Monitor for 640 X 480 resolution. Later iterations included motion text, ping-pong game and color control. HONORS AND AFFILIATIONS

Awarded Excellence in Academics for my under-graduate degree during all my semesters.

Vice-Chairman of IEEE CBIT-Student Chapter: responsible for weekly presentations and organizing workshops.

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