| Resume alert | Resumes 21 - 30 of 33 |
physical design engineer
Hyderabad, Telangana, 500079, India
... Participated in the block level full chip timing closure (STA) of multi-million gate ASICs. Developed PERL/Tcl scripts to handle various requirements of algorithms and data manipulation Gained good Knowledge in subjects like Digital design backend, ... - 2014 Oct 07
... Participated in the block level full chip timing closure (STA) of multi-million gate ASICs. Developed PERL/Tcl scripts to handle various requirements of algorithms and data manipulation Gained good Knowledge in subjects like Digital design backend, ... - 2014 Oct 07
Product Application Engineer
Hyderabad, Telangana, 500003, India
... SKILL SET CORE STRENGTH Digital Electronics, Digital Circuit Design, Timing Analysis (STA and DTA), CMOS, FPGA Design Flow. SOFTWARE SKILLS Verilog, VHDL, Basic knowledge of system Verilog, C language. HANDS ON WORKING KNOWLEDGE FPGA Architecture v4 ... - 2014 Sep 24
... SKILL SET CORE STRENGTH Digital Electronics, Digital Circuit Design, Timing Analysis (STA and DTA), CMOS, FPGA Design Flow. SOFTWARE SKILLS Verilog, VHDL, Basic knowledge of system Verilog, C language. HANDS ON WORKING KNOWLEDGE FPGA Architecture v4 ... - 2014 Sep 24
Pvt Ltd Quality
Hyderabad, AP, India
... > Semiconductor technologies: Physical design, Verification, Logic Design, STA, Processor, Floor Planning, Routing, Verilog, VHDL, TCL, SKILL, Spec man, Vera > Embedded / Firmware Technologies: I/O Hardware, Servers, modeling, Assembly, C++, and ... - 2014 Feb 28
... > Semiconductor technologies: Physical design, Verification, Logic Design, STA, Processor, Floor Planning, Routing, Verilog, VHDL, TCL, SKILL, Spec man, Vera > Embedded / Firmware Technologies: I/O Hardware, Servers, modeling, Assembly, C++, and ... - 2014 Feb 28
IOS fresher
Hyderabad, AP, India
... Shabi sta Anjum - 2013 Dec 31
... Shabi sta Anjum - 2013 Dec 31
Project Manager Electrical Engineer
HYD, AP, India
... > Laying of all electrical cables both armoured and unarmoured for LV and MV (STA,SWA,XLPE,PVC) underground cabling, bus duct and raising mains as per approved shop drawings. > Working experience in telephone and public address system networks in ... - 2013 Jul 18
... > Laying of all electrical cables both armoured and unarmoured for LV and MV (STA,SWA,XLPE,PVC) underground cabling, bus duct and raising mains as per approved shop drawings. > Working experience in telephone and public address system networks in ... - 2013 Jul 18
Project Design
Hyderabad, AP, India
... Clocks : 17 Frequency : 200 MHz Utilization : 87.3 % Technology / Layers : TSMC 0.13 microns / 5 Metal Layers Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing Analysis, CTS, Detail Routing, RC extract, STA. ... - 2013 May 24
... Clocks : 17 Frequency : 200 MHz Utilization : 87.3 % Technology / Layers : TSMC 0.13 microns / 5 Metal Layers Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing Analysis, CTS, Detail Routing, RC extract, STA. ... - 2013 May 24
Project Manager
Hyderabad, AP, India
... MS Visio, Quality Centre and MPP | |Performance Testing Tools |Load Runner, Web Load, OPEN STA | |Automation Testing Tools |Win Runner, QTP, Selenium | |Bug Tracking Tools |QC, Bugzilla, Mantis, Jira, WPBN | | |Qualificatio| | | |ns | | |1998 |B. ... - 2012 Nov 22
... MS Visio, Quality Centre and MPP | |Performance Testing Tools |Load Runner, Web Load, OPEN STA | |Automation Testing Tools |Win Runner, QTP, Selenium | |Bug Tracking Tools |QC, Bugzilla, Mantis, Jira, WPBN | | |Qualificatio| | | |ns | | |1998 |B. ... - 2012 Nov 22
Design Engineer Objective
Hyderabad, AP, India
... • Participated in the FUB (Multi million gate ASIC blocks) level and box level timing closure (STA) by fixing all kinds of timing and violations were fixed using ECO reports Physical Verification DRC & LVS for TOPLEVEL using Calibre. BLOCK2 (Double ... - 2012 Sep 18
... • Participated in the FUB (Multi million gate ASIC blocks) level and box level timing closure (STA) by fixing all kinds of timing and violations were fixed using ECO reports Physical Verification DRC & LVS for TOPLEVEL using Calibre. BLOCK2 (Double ... - 2012 Sep 18
Project Design
Hyderabad, AP, 500072, India
... Software : CATIA V5 R19 Duration : 12 weeks (May 2012 – July 2011) Team Size : 4 Description : Modeling of Bulkhead caps, Cap Angles @ Ramp sta 2 & 4. • Modeling of Fastener points & vectors between Ramp sta 0-4.. • Modeling of Floor panels as ... - 2012 Aug 22
... Software : CATIA V5 R19 Duration : 12 weeks (May 2012 – July 2011) Team Size : 4 Description : Modeling of Bulkhead caps, Cap Angles @ Ramp sta 2 & 4. • Modeling of Fastener points & vectors between Ramp sta 0-4.. • Modeling of Floor panels as ... - 2012 Aug 22
Design Engineer
Hyderabad, AP, 500051, India
... Hands on experience on ASIC PHYSICAL DESIGN flow, Floor planning, Power planning, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), IR drop analysis, Scan chain reordering and Top/Block level ECO implementation. . DRC-LVS ... - 2012 Aug 15
... Hands on experience on ASIC PHYSICAL DESIGN flow, Floor planning, Power planning, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), IR drop analysis, Scan chain reordering and Top/Block level ECO implementation. . DRC-LVS ... - 2012 Aug 15