Email:firstname.lastname@example.org Mobile No: +91-994*******
To obtain a position as a PHYSICAL DESIGN engineer with provision for
innovation and creativity in a growing and quality-focused organization for
getting a right start and quality exposure.
. Worked as Assistant Professor for one year and guided students in the
completion of their VLSI projects.
. Worked as Co-ordinator for VLSI lab and handled related tools.
. Well experienced in VLSI, Electronic devices and Digital design
. M.Tech (VLSI System Design) from Indur Institute of Engineering and
Technology, JNTU Hyderabad(2012) with 78%
. B.Tech (Electronics and comm.)from Medak College of Engineering and
Technology, JNTU Hyderabad(2009) with 75%
. Intermediate from SVB Junior College, Board of Intermediate
Education, Hyderabad(2005) with 91.50%
. SSC from ZPHS, Board of Secondary Education, Hyderabad(2005) with 86%
. Completed PG Diploma in VLSI physical design at Shastra Micro System,
. Period: 6 months.
. Tool used: Synopsys IC compiler.
. Hands on experience on ASIC PHYSICAL DESIGN flow, Floor planning,
Power planning, Placement, Clock Tree Synthesis (CTS), Routing, Static
Timing Analysis (STA), IR drop analysis, Scan chain reordering and
Top/Block level ECO implementation.
. DRC-LVS closure, antenna fixing, signal integrity.
. Good experience in writing scripts using PERL, TCL and C shell.
. Hands on knowledge about SYSNOPSIS IC Compiler.
. Hands on experience in using C programming language.
Presentations and Workshops:
. Paper Presentation on VLSI DESIGN during Post Graduation.
. Attended ORIENTATION COURSE-17 conducted by UGC Academic staff
. Trained by IEG-JKC during graduation.
. Participated in the VLSI workshop conducted by FALCON electronics.
Title: Design of RISC full chip using 130nm Technology
Roles and Responsible: Floor planning, Power planning, Placement, Clock
Tree Synthesis, Routing and Physical verification of RISC chip. The
challenges were achieved area and power limitations given with a positive
slack in net list and skew balancing to meet the timing. This RISC full
chip was implemented with a gate count of 60k, 10 macros and 6 metal layers
were used for routing. This was implemented on a 130nm technology.
Challenges: Macro placement was critical, resolving placement congestion
and timing issues.
Clock frequency : 300MHz
Nets : 200k
Operating Voltage : 1.3V
Tools Used : IC Compiler (Duration: 3 months)
Title: Efficient On-Chip Cross Talk Avoidance CODEC Design
Roles and Responsible: Interconnect delay has become a limiting factor for
circuit performance in deep sub-micrometer designs. Different crosstalk
avoidance coding schemes have been proposed to boost the bus speed and/or
reduce the overall energy consumption. This is mainly due to the nonlinear
nature of the crosstalk avoidance codes (CAC). This work presents
guidelines for the CODEC design of the "forbidden pattern free crosstalk
avoidance code" (FPF-CAC). I analyze the properties of the FPF-CAC and show
that mathematically, a mapping scheme exists based on the representation of
numbers in the Fibonacci numeral system.
Plat form: Verilog Simulation: Modelsim Synthesis: Xilinx9.0
. Selected for "Mahindra Satyam" during graduation (2008-2009).
. Class topper from School level to Post Graduation.
Father's name : A. Pochaiah
Date of birth : 26 MAY 1988
Marital status : Single
Languages known : English, Telugu, Hindi
Passport : G8329025
Permanent address : H.NO:2-26, Etigaddakistapur (Vil),
Thoguta (Mdl), Medak (Dist.), Andhra
I hereby declare that the above furnished information is true and
correct to the best of my knowledge.