| Resume alert | Resumes 11 - 20 of 33 |
Civil Engineering C
Hyderabad, Telangana, India
... I nte rns hipo nto tal sta tio nfo ramo nth CURRI CULARACTI VITES : Wo rke dasCO- ORDI NATORf orS IDDHARTHJ UBI LATI ONe ven t PERS ONALTRAI TS: Ia mRe spo nsi bl epe rso n,Ad apt abl efo ran yne wsi tua tio nan dno tea sil yruf fl ed. ... - 2020 Oct 08
... I nte rns hipo nto tal sta tio nfo ramo nth CURRI CULARACTI VITES : Wo rke dasCO- ORDI NATORf orS IDDHARTHJ UBI LATI ONe ven t PERS ONALTRAI TS: Ia mRe spo nsi bl epe rso n,Ad apt abl efo ran yne wsi tua tio nan dno tea sil yruf fl ed. ... - 2020 Oct 08
Geotechnical Engineer
Hyderabad, Telangana, India
... Manager (Geotechnical), Railways Division Duration Working from Dec’2016 - Till date Responsibilities Handled Design/review of Foundations, Embankment (Rail and Earthen), Rock slope sta- bility, Ground Improvement techniques, Reinforced Soil Walls ... - 2020 Jul 31
... Manager (Geotechnical), Railways Division Duration Working from Dec’2016 - Till date Responsibilities Handled Design/review of Foundations, Embankment (Rail and Earthen), Rock slope sta- bility, Ground Improvement techniques, Reinforced Soil Walls ... - 2020 Jul 31
Civil Engineering Engineer
Hyderabad, Telangana, India
... Marking of brick work @ vomitory staircases, moat staircases, sta&stb Staircases Areas as per drawings. 9. Coordinate to the planning dept. 10. Control of man power and utilization of other works. 11. Taking of RLs and levels @ IPS flooring and Moat ... - 2020 Jul 15
... Marking of brick work @ vomitory staircases, moat staircases, sta&stb Staircases Areas as per drawings. 9. Coordinate to the planning dept. 10. Control of man power and utilization of other works. 11. Taking of RLs and levels @ IPS flooring and Moat ... - 2020 Jul 15
Network Test Engineer
Hyderabad, Telangana, India
... Responsible for testing related to STA-IOT, MMH-IOT (Marvell Mobile Hotspot), and Simultaneous Operation (STA+MMH) related to Marvell Products. Managed a team of size 4. Trained team members in technical and QA procedures. Drafting, reviewing and ... - 2020 Feb 20
... Responsible for testing related to STA-IOT, MMH-IOT (Marvell Mobile Hotspot), and Simultaneous Operation (STA+MMH) related to Marvell Products. Managed a team of size 4. Trained team members in technical and QA procedures. Drafting, reviewing and ... - 2020 Feb 20
Design Engineer Assistant
Malkajgiri, Telangana, India
... Experience in Static Timing Analysis (STA) using PrimeTime tool for analyzing timing reports with OCV, MCMM, CRPR, Clock skew. Languages and Tools Hardware Languages :- Verilog HDL, VHDL Scripting Languages :- Linux Shell Scripting, Introduction to ... - 2019 Dec 27
... Experience in Static Timing Analysis (STA) using PrimeTime tool for analyzing timing reports with OCV, MCMM, CRPR, Clock skew. Languages and Tools Hardware Languages :- Verilog HDL, VHDL Scripting Languages :- Linux Shell Scripting, Introduction to ... - 2019 Dec 27
Engineering Inplant Training
Hyderabad, Telangana, India
... ASSOCIATED PROFESSIONAL BODIES AND MEMBERSHIPS Engineers Without Borders – India (Membership No: STA 101) Society of Automotive Engineers - India (Membership No: 716*******). SKILLS CATIA Solid Works ANSYS Auto CAD CNC Programming (Basic) Mat lab ... - 2019 Aug 11
... ASSOCIATED PROFESSIONAL BODIES AND MEMBERSHIPS Engineers Without Borders – India (Membership No: STA 101) Society of Automotive Engineers - India (Membership No: 716*******). SKILLS CATIA Solid Works ANSYS Auto CAD CNC Programming (Basic) Mat lab ... - 2019 Aug 11
Engineering High School
Hyderabad, Telangana, India
... Cer fica on: -Auto CAD -Total sta on Areas of interests: -ENVIRONMENTAL ENGINEERING -CONCRETE TECHNOLOGY Achievements: -Got 2nd prize in project expo -winning the inter college cricket tournament under my captaincy Field Experience: -one day ... - 2017 Nov 04
... Cer fica on: -Auto CAD -Total sta on Areas of interests: -ENVIRONMENTAL ENGINEERING -CONCRETE TECHNOLOGY Achievements: -Got 2nd prize in project expo -winning the inter college cricket tournament under my captaincy Field Experience: -one day ... - 2017 Nov 04
Product Development Design
Hyderabad, Telangana, India
... and CMOS layout, RF IC Design ( LNA,PLL,PA, Phase Noise, gain, Mixer), Wiring issues, Timing issues in digital circuits, STA, RTL Circuit Design, Memory Design and Characterization, Digital Design Concepts & Digital system design using Verilog ... - 2017 Apr 21
... and CMOS layout, RF IC Design ( LNA,PLL,PA, Phase Noise, gain, Mixer), Wiring issues, Timing issues in digital circuits, STA, RTL Circuit Design, Memory Design and Characterization, Digital Design Concepts & Digital system design using Verilog ... - 2017 Apr 21
Design Data
Hyderabad, Telangana, India
... TECHNICAL SKILLS Knowledge on VLSI Fundamentals, ASIC Flow, Digital Design, Physical Design, Low power Techniques, STA. Hardware languages : Verilog, Basics of system verilog. Programming Languages : Basics in C. Scripting languages : Basics in ... - 2016 Apr 30
... TECHNICAL SKILLS Knowledge on VLSI Fundamentals, ASIC Flow, Digital Design, Physical Design, Low power Techniques, STA. Hardware languages : Verilog, Basics of system verilog. Programming Languages : Basics in C. Scripting languages : Basics in ... - 2016 Apr 30
Design Manager
Hyderabad, Telangana, 500057, India
... 2008 to 2012 SKILLS Embedded c, C & C++ Programming, Verilog and VHDL Programming, System Verilog, ASIC, SOC,VMM, OVM,UVM, STA,RTL Design, Design Verification, Synthesis, Digital Design PUBLICATIONS Design Of Ternary Logic Gates Using CNTFET http:/ ... - 2015 Aug 10
... 2008 to 2012 SKILLS Embedded c, C & C++ Programming, Verilog and VHDL Programming, System Verilog, ASIC, SOC,VMM, OVM,UVM, STA,RTL Design, Design Verification, Synthesis, Digital Design PUBLICATIONS Design Of Ternary Logic Gates Using CNTFET http:/ ... - 2015 Aug 10