Design Engineer Objective

CURRICULUM VITAE

NAME : Y.SATHISH

PHONE NO : +91-994*******

EMAIL ID : *******.******@*****.***

________________________________________

Objective:

To work in a challenging environment demanding all my skills and efforts to explore and adapt myself in different fields, and realize my potential and contribute to the development of organization with impressive performance.

Professional experience:

• 1.4 years of experience in VLSI Physical Design

• Worked on ASIC physical design flow in 32nm, 40nm & 65nm technologies

• Familiar in backend flow: Floor Planning, Place & Route, Clock Tree Synthesis, Timing Closure.

• Presently working as Physical Design Engineer at First Pass Semiconductors pvt.lt, HYD (from 2nd of May 2011 to current date)

TOOLS FAMILIAR WITH:

Floor plan, Place & Route : SOC Encounter

Timing Analysis : ETS

Signal Integrity Analysis : Celtic, ETS

Logic Synthesis : RTL-Compiler

Physical Verification : Calibre

Educational Qualifications:

PG Diploma in VLSI ASIC Design Course From Institute of Silicon Systems, Hyderabad

Bachelor of Engineering in Electronics & Communication Engineering

(2006-2010) Vivekananda institute of... (Affiliated to JNTU, Hyd)

EXPERIENCE AND PROJECT DETAILS:

BLOCK1 (Design – PCI)

Objective : Timing Driven Layout

Gate count/Area : 1, 85,475/ 968820.2 um^2

Macros /STD Cells : 5/41935

No. of Clocks : 13

Frequency : 50MHz

Technology : 32nm

Roles and Responsibilities:

• Worked on physical design (Floor Planning, I/O planning, Power planning, Placement, CTS, Routing, Parasitic Extraction, SI analysis) for various ASICs.

• Participated in the FUB (Multi million gate ASIC blocks) level and box level timing closure (STA) by fixing all kinds of timing and violations were fixed using ECO reports Physical Verification DRC & LVS for TOPLEVEL using Calibre.

BLOCK2 (Double Edge Data Receiver)

Tools : SOC Encounter, QRC& ETS.

Gate count : 198K

No. of Clocks : 3

Frequency : 200 MHz

Technology : UMC 0.65 micron

Roles and Responsibilities:

Performing sanity check, Design import, Floor Plan, Power Plan, Placement, Trail Route, Power Analysis, RC Extract, CTS, Adding Filler Cells, Timing analysis.

BLOCK3 (MTV1)

Technology : 40nm

Tools : SOC Encounter, QRC, Celtic.

Gate count/Area : 1.2M / 1873836.1 um^2

Macros : 5

No. of Clocks : 4

Frequency : 125MHz

Role : Floor planning & placement, clock tree

Synthesis, optimization, SI driven routing, RC

Extraction, STA, crosstalk analysis

Challenges faced : Congested and timing critical.

Personal Profile:

Name : Y.Sathish

Father’s Name : Sattaiah

Permanent Address : NTPC, Jyothinagar, Ramagundam,

(Dist): Karimnagar, PIN CODE: 505 215, INDIA

Gender : Male

Date of Birth : 17-01-1988

Marital Status : Single

Nationality : Indian

Languages Known : English, Telugu, and Hindi

Declaration:

I do hereby declare that the particulars of information and facts stated here in above are true, correct and complete to the best of my knowledge and belief.

Date:

Place: Hyderabad (Y SATHISH)

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