| Resume alert | Resumes 31 - 40 of 2011 |
Project Manager North Carolina
Albany, NY
JON L VINCZE P: 469-***-**** ad3ha4@r.postjobfree.com EDUCATION Doctorate of Osteopathic Medicine Marian University College of Osteopathic Medicine, Indianapolis, IN Bachelors of Arts in Behavioral Neuroscience & Chemistry University of San Diego... - Feb 08
JON L VINCZE P: 469-***-**** ad3ha4@r.postjobfree.com EDUCATION Doctorate of Osteopathic Medicine Marian University College of Osteopathic Medicine, Indianapolis, IN Bachelors of Arts in Behavioral Neuroscience & Chemistry University of San Diego... - Feb 08
Verification Engineer Fpga Design
Santa Clara, CA, 95050
... Excellent Verilog/SystemVerilog, VHDL RTL coding skill Extensive working knowledge of digital logic, analog circuit and mixed-signal design Proficiency in C, Matlab/Simulink and Python programming Working knowledge of Vitis HLS Experience with AXI4 ... - Feb 06
... Excellent Verilog/SystemVerilog, VHDL RTL coding skill Extensive working knowledge of digital logic, analog circuit and mixed-signal design Proficiency in C, Matlab/Simulink and Python programming Working knowledge of Vitis HLS Experience with AXI4 ... - Feb 06
Software Engineer Cloud Infrastructure
Fort Worth, TX
... ● Collaborated closely with senior engineers in the rigorous process of RTL bug identification and resolution, enhancing product integrity. ● Contributed to refining and optimizing existing hardware verification methodologies, leading to more ... - Feb 03
... ● Collaborated closely with senior engineers in the rigorous process of RTL bug identification and resolution, enhancing product integrity. ● Contributed to refining and optimizing existing hardware verification methodologies, leading to more ... - Feb 03
Software Engineer
Warren, NJ
... and the Federal Reserve Bank • Technology domain: OpenVMS, Windows NT, Transactional Message Processing, ANSI/VAX C, VAX C/RTL, DCL, SQL, VB, HTML, JavaScript, TCP/IP, X.25 Co-founder / CTO / Chief Architect – IP Telecom CommRad Communications / ... - Feb 01
... and the Federal Reserve Bank • Technology domain: OpenVMS, Windows NT, Transactional Message Processing, ANSI/VAX C, VAX C/RTL, DCL, SQL, VB, HTML, JavaScript, TCP/IP, X.25 Co-founder / CTO / Chief Architect – IP Telecom CommRad Communications / ... - Feb 01
Knowing basic knowledge of verification languages such as Verilog
Ho Chi Minh City, Vietnam
... - Using simulation tools, debug tools to debug functional errors in RTL models. SKILL Simulates Tools: Design Compiler, VCS,Verdi,Jasper Gold, Model Sim, Quartus. Scripting languages: Perl, Shell and Python. Formal veri cation: Working experience ... - Feb 01
... - Using simulation tools, debug tools to debug functional errors in RTL models. SKILL Simulates Tools: Design Compiler, VCS,Verdi,Jasper Gold, Model Sim, Quartus. Scripting languages: Perl, Shell and Python. Formal veri cation: Working experience ... - Feb 01
Project Manager Data Analyst
Thornhill, ON, Canada
... Had worked closely with SAP client team to establish a process to connect RTL landscape with SAP legacy system using IBM Infosphere DataStage SAP packs and this process is widely used for different Roll outs in SAP migration projects. Had led team ... - Jan 31
... Had worked closely with SAP client team to establish a process to connect RTL landscape with SAP legacy system using IBM Infosphere DataStage SAP packs and this process is widely used for different Roll outs in SAP migration projects. Had led team ... - Jan 31
C++ Software Developer
Dover, MA, 02030
... I also had to debug issues found in the user designs (Soc, Asic, Fpga) written in RTL/GA by using SystemVerilog, SV assertions, Vpi/Pli/Cli/Dki, coverage. The changes helped the company to secure better contracts with customers like Apple, Intel, ... - Jan 29
... I also had to debug issues found in the user designs (Soc, Asic, Fpga) written in RTL/GA by using SystemVerilog, SV assertions, Vpi/Pli/Cli/Dki, coverage. The changes helped the company to secure better contracts with customers like Apple, Intel, ... - Jan 29
B C 1 0
Indianapolis, IN
... 'V 踦 /dK TI U 2o Z2t )P+o e Z Ɋ P ͭ F Ȕ sEZ ece _ A +̏ 9 1 b w G, MXV LE k cs 7@c y ) 3x 2 c q y m u TW\F h1 ̕ 2 ݯ D a K Dlj Rtl In M us jaJ G B S W yB ~nb 1 P Xc *ŨO \P R H ֔1 :H ̫X] H ޅ W 07 v'-Y ʟN !w2 vO 聋 D P RuS q P2 &D Ṕ巷 J _ бo C ӳ Ꜳ sW p o ... - Jan 25
... 'V 踦 /dK TI U 2o Z2t )P+o e Z Ɋ P ͭ F Ȕ sEZ ece _ A +̏ 9 1 b w G, MXV LE k cs 7@c y ) 3x 2 c q y m u TW\F h1 ̕ 2 ݯ D a K Dlj Rtl In M us jaJ G B S W yB ~nb 1 P Xc *ŨO \P R H ֔1 :H ̫X] H ޅ W 07 v'-Y ʟN !w2 vO 聋 D P RuS q P2 &D Ṕ巷 J _ бo C ӳ Ꜳ sW p o ... - Jan 25
Consumer Products Embedded Software
Los Gatos, CA
... 2002 – 2008 Verification Architect Nvidia Santa Clara CA Led 17 software engineers developing C model and Verilog RTL verification infrastructure of 50+ million gate graphics integrated circuits. Supported teams at multiple sites in U.S. and India. ... - Jan 19
... 2002 – 2008 Verification Architect Nvidia Santa Clara CA Led 17 software engineers developing C model and Verilog RTL verification infrastructure of 50+ million gate graphics integrated circuits. Supported teams at multiple sites in U.S. and India. ... - Jan 19
Electrical Engineering Verification Engineer
Long Beach, CA
... CERTIFICATIONS: PHYSICAL DESIGN ENGINEER TRAINING Course via VLSIGuru (06/2023 – 12/2023) • Hands-on experience in fundamental concepts and advanced techniques in digital design and implementation, including synthesis, RTL analysis, timing ... - Jan 18
... CERTIFICATIONS: PHYSICAL DESIGN ENGINEER TRAINING Course via VLSIGuru (06/2023 – 12/2023) • Hands-on experience in fundamental concepts and advanced techniques in digital design and implementation, including synthesis, RTL analysis, timing ... - Jan 18