YOGITHA SHAMSUNDER

**** * ******* ***, *** *** Long Beach, CA 90815 +1-562-***-**** ad2wga@r.postjobfree.com www.linkedin.com/in/yogitha-shamsunder

EDUCATION:

CALIFORNIA STATE UNIVERSITY LONG BEACH (Long Beach, California) (08/2021-12/2023)

• MASTER OF SCIENCE IN ELECTRICAL ENGINEERING (GPA 3.44/4.0)

• RELATED COURSEWORK: Mixed Signal IC Design, Analog Signal Processing, VLSI Design, CMOS Electronics, Microfabrication and Nanotechnology.

SYMBIOSIS INSTITUTE OF TECHNOLOGY (Pune, India) (07/2017-06/2021)

• BACHELOR OF TECHNOLOGY IN ELECTRONICS AND TELECOMMUNICATIONS (GPA 7.9/10)

• RELATED COURSEWORK: VLSI Design, Advanced FPGA Design, CMOS VLSI Design, Analog Circuit Design, Semiconductor Devices and Circuit Application, Printed Circuit Board Design. EXPERIENCE:

DEXCEL ELECTRONICS DESIGNS PVT. LTD (Bangalore, India) FPGA DESIGN ENGINEER INTERN (01/2020 - 04/2020)

• Assisted a team of 8 FPGA professionals by conducting test-runs on the project module and debugging code to eliminate errors, enhancing processing time by 15%.

• Optimized team efficiency by creating block diagrams and flowcharts using Microsoft Visio, resulting in a reduction of 5 hours of designing time per week.

• Operated on design tools such as Xilinx Vivado, Xilinx ISE, ModelSim, and Quartus Prime, to complete 2 minor projects.

• Maintained accurate documentation throughout the project lifecycle, including design specifications, updating test reports, and user manuals.

• Prepared weekly summary reports to update team lead and university internship mentor on project progress and achieved approval for 20+ reports.

PROJECTS:

DESIGN A CHARGE PULSE GENERATOR USING CADENCE VIRTUOSO (08/2022 – 12/2022)

• Operated on Cadence Virtuoso to design an Operational Amplifier circuit which included creating a library, cell, symbol and testbench and then analyzed the waveform over a course of 6 lab sessions.

• Built a Charge Pulse Generator circuit for a CMOS-based Optical Sensor using Cadence design tools by performing a literature review of over 13 research papers.

• Raised the sensitivity of the circuit for background light detection by 17% through rigorous simulation and testing. DESIGN A STANDARD CELL LIBRARY USING MICROWIND AND DSCH (08/2021 – 12/2021)

• Created a standard cell library consisting of 6 basic gates and universal gates using Microwind design tools.

• Built a 4-bit Up-Down Counter and an 8-bit Multiplexer using the standard cells and simulated the designs using DSCH. Analyzed the simulation results to validate the functionality and performance of the circuits. DESIGN I/O RINGS USING XILINX ISE AND DIGILENT FPGA BOARD (SPARTAN 6) (08/2021 – 12/2021)

• Designed Input/Output (I/O) rings for a Counter and Multiplexer using Xilinx design tools. Verified and tested the functionality of the designs by dumping the code onto a Spartan 6 FPGA board. DESIGN FINITE STATE MACHINES USING XILINX VIVADO (01/2021 – 04/2021)

• Implemented a MOD 30 counter, FSM Designs, Power optimization circuit, high throughput and low latency circuit, 4-way traffic light control circuit and a coffee vending machine circuit using Verilog. BUILD A CIRCUIT ON THE PCB WITH THE HELP OF KICAD (01/2021 – 04/2021)

• Designed and simulated a PCB circuit for a solar-powered laptop charger using KiCad and implementing the hardware on breadboard for prototyping purposes.

CERTIFICATIONS:

PHYSICAL DESIGN ENGINEER TRAINING Course via VLSIGuru (06/2023 – 12/2023)

• Hands-on experience in fundamental concepts and advanced techniques in digital design and implementation, including synthesis, RTL analysis, timing constraints, clock tree synthesis, power planning, floor planning, and various optimization strategies.

• It also explores multi-voltage design, UPF, and addresses challenges in Design For Manufacturability (DFM) with topics such as antenna rules, critical area analysis, wire spreading, and parasitic extraction. Projects encompassing the entire design flow, from input files to GDSII export, demonstrate practical application of the learned concepts.