Victor Muravyov

Mobile: 857-***-**** E-mail: ad27my@r.postjobfree.com Addr: Dover, MA 02030

linkedin.com/in/victor-muravyov-994b4528

SOFTWARE DEVELOPER

Software Architect and Developer with extensive US-based work experience in architecting, designing and developing complex software solutions across a variety of applications and languages, abstract thinking, algorithm design and team leading. Strong mathematical background and knowledge of compiler technologies; Extensive experience with large complex code base, agile development, and system design life cycle issues; Solid understanding of object-oriented design principles and patterns. Languages/Tools: C, C++11, Visual C++, Visual C#, STL, Boost, Lex/Yacc, Flex/Bison, System Verilog, SVA, VHDL, PSL, Verilog-AMS, Objective-C, Xcode on Mac OS, ANTLR-4, Linux, Petalinux, Unix, Eclipse IDE, Python + machine learning, STM32 nucleo-64 (ARM Cortex M4), STM32CubeIDE, Qt/QtCreator, Gnu (g++, gcc, gdb, valgrind, lex, yacc, git), VisualStudio Operating Systems: Linux Red Hat/Ubuntu/, Petalinux, UNIX, iOS, Mac OS, Windows GUI Development: X-Windows/Motif, Qt, GPR, Xcode Interface Builder DB Development: Microsoft Sequel, ODBC, SQL

EXPERIENCE

Mercury Systems contract Andover, MA 03/2022 - 09/2023 Provisioning software for Fpga (C/C++) for chip provisioning, monitoring,security C# GUI to visualize the chip provisioning.

Tools to allow use of DFDL language processing on the Fpga (C/C++) Added new functionality to the proprietary layer on top of UVM (verification methodology) for Fpga (pcie) verification in multi-threading. Petalinux, QuestaSim, ModelSim, Git Leidos short-term contract Tewksbury, MA 07/2021 – 09/2021 Porting parts of the airport luggage security system from Scientific Linux to Red-Hat for government certification.

This transition required a different approach of invoking the anti-virus protection of USB devices. C++, STL, Linux, Synergy

Tools for Stock-Market analysis self-employed 03/2020 – 06/2021 Working on tools for predictive analytics in C++, Python. Supervised and unsupervised machine learning, pandas, NumPy, mathplotlib Cadence Design Systems, Chelmsford/Burlington MA 04/2015 – 02/2020 Principal R&D Engineer

Developed and re-architected/re-designed various components for the System Verilog and Analog Mixed Signal handwritten compiler-simulator XCELIUM (Electronic Design Automation industry) in order to enforce the strict compliance with language IEEE standard and make it more extend-able to support new language and user requested constructs and features, graph based reachability and connectivity analysis. The SystemVerilog language is consistently evolving in the direction of C++ and that requires introduction of new and more elaborate features which is demanded by the customers. Providing them often represents a challenge for the existing compiler design and architecture and requires re-engineering of the core. By doing that I have significantly improved and modernized the old code base and architecture

(C++11 objects replacing complex logic implemented as re-entrant C code controlled by many globals). These changes required to understand the current logic and the underlying finite state automatons, to identify the bottlenecks in the architecture resulting in improved solutions and clearing the path to support the upcoming new constructs and features in modern SystemVerilog. Re-architecting and deep re- factoring resulted in significant improvement in code stability, quality, overall performance and clarity in the implementation of the compiler components. Also worked on few modern SystemVerilog language extensions/constructs, fixed existing bugs in the code and behavioral derivations from the Language Reference Manual discovered by the customers. I also had to debug issues found in the user designs

(Soc, Asic, Fpga) written in RTL/GA by using SystemVerilog, SV assertions, Vpi/Pli/Cli/Dki, coverage. The changes helped the company to secure better contracts with customers like Apple, Intel, Samsung, AMD, ARM, Huawei, etc. against the competition.

Most of the work was done in C++11 using design patterns, graph analysis, templates and modern C++ features like lambdas, STL, boost. Writing proposals, design and functional specs. Synopsys, Marlboro, MA 01/1997 – 04/2015

Senior Staff R&D Engineer

Architected/designed/developed various components for the then leading Electronic Design Automation industry (EDA) System Verilog and Vhdl compiler-simulator VCS. Added new and modified existing components of this very complex system to allow support of new language constructs, automatic analysis and instrumentation of given user designs; worked on parsing, elaboration, code generation, and simulation tools with the goal of providing functional and behavioral design verification.

• Automatic identification, extraction and code instrumentation of finite state machines hidden in their designs based on design code static analysis, their behavioral analysis during simulation (C++, C, Lex, Yacc, Linux), design test suite code coverage for automata

• Functional coverage, timing and event sequence based assertions (temporal assertions) (C++, C, Linux)

• Post-simulation replay system helping users to form sets of temporal assertions directed to finding functional bugs (C++, C, Linux)

• Automatic user design instrumentation, monitoring and reporting of various kinds of code coverage, design test grading, handling of simulation races and glitches (congruency), propagation of undefined values (C++, C, STL, Lex, Yacc, Linux)

• Hierarchical target control in coverage, temporal assertions and other analysis during design compilation and simulation (C++, C, Linux)

• Support constructs inheritance, new features in SystemVerilog, VHDL, PSL languages (C++, C, Lex, Yacc, Linux)

• Endian independent run-time databases to allow parallel simulation on various machines/platforms

(C++, C, Linux)

• New language features and constructs in parser (Lex, Yacc, Linux)

• Code generation and optimizations, code instrumentation for run-time profiling (C++, C, Linux)

• Report generations in HTML, text, graphical user interfaces (C++, C, X-Windows/Motif, Qt, Linux)

• Writing proposals and functional specs, close interaction with customers to form and finalize scope and requirements

Mobile Developer (in my free time from main Synopsys work) 2011 – 2015 Independent iOS developer with over 3 years of experience in writing complex, object-oriented source code in Objective-C and Xcode. I have developed mobile healthcare applications to meet the needs of diabetes patients. These apps offered patients an intuitive interface for tracking medications, patient- physician communications, alerts, reporting and data analytics. Those were available in the Apple App Store. (Objective-C, Xcode, Interface Builder, iOS/Mac OS) and were downloaded by over 2000 users. Stopped this enterprice because my IMac became not up-gradable to the next version of MacOs and Xcode

System Architect at American Student Assistance Boston, MA 1995-1997 Designed and developed a rules-based engine for the “Loan Guarantee” system.

• A scripting language and interpreter for expressing business rules governing student loan life cycles (Visual C++, Windows)

• Build a "proof of concept" system prototype (Visual C++, Windows, MFC, RPC, ODBC, SQL)

• Made finite state automata representing the rules engine, interfaces, flow model, GUI (Visual C++, Windows)

• Managed a small team of engineers, worked with the company’s business units to define the system’s business rules

Project Program Analyst at UNISYS Cambridge, MA 1990-1995 Designed and developed air traffic control tools for the Federal Aviation Administration.

• Various components for the multi-layered air traffic display system, including zoom-able maps overlaid by real-time airplane positions, flight paths, weather patterns and flight information (C, C++, Unix, X-Windows/Motif, initially Pascal, Aegis, graphic primitives)

• An engine and GUI for an interactive “Air Traffic Simulator” designed to predict, emulate and model resolutions for traffic loads and airport congestion (C, Unix, X-Windows/Motif)

• An interpretive visual prototype builder for real-time air traffic data analytics and statistics. Key features included ability to overlay real-time data with analytics, various data visualization dashboards, and statistical analysis application (first, developed using Pascal and GPR, then in C, C++ and X-Windows/Motif)

Prior Experience in USSR - computerized lung and heart modeling in nuclear medicine, thermo- dynamical models using numerical mathematics on Fortran, PL-1, Algol, assembler RT11/PDP-11 clone, and assembler OS/IBM – 360/370 clone. Visualization was done through the low level monitor programming in RT11 assembler

EDUCATION & OTHER

Russian State Technological University named after K.E. Tsiolkovsky (MATI) BS, MS - Aeronautical Engineering

• US Citizen since 1991

• Fluent in English, native speaker in Russian, reading and writing in German

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