| Resume alert | Resumes 21 - 30 of 83 |
Software Engineer Support
Queensville, ON, L0G 1R0, Canada
... Designed modules for Open Source FFMPEG for Close Capture subtitle format with full support for main video stream formats and containers Designed and developed internal Linux and network oriented test and debug application intend for FPGA ... - 2019 Mar 08
... Designed modules for Open Source FFMPEG for Close Capture subtitle format with full support for main video stream formats and containers Designed and developed internal Linux and network oriented test and debug application intend for FPGA ... - 2019 Mar 08
Sr Electronics Engineer, Engineering
Vaughan, ON, L4L 8R9, Canada
... NOISE & POWER / HIGH SPEED, RF & POWER * PRODUCT DESIGN / TESTING / VERIFICATION * DEVICES, SENSORS, CIRCUITS ADC/DAC, PROCESSORS, FPGA, FIRMWARE, INTERFACES, SYSTEMS (0.1Hz-110GHz, nV-kV, fA-kA, pW-kW, UV-IR) * MATHEMATICS / MODELING, ANALYSES AND ... - 2019 Feb 01
... NOISE & POWER / HIGH SPEED, RF & POWER * PRODUCT DESIGN / TESTING / VERIFICATION * DEVICES, SENSORS, CIRCUITS ADC/DAC, PROCESSORS, FPGA, FIRMWARE, INTERFACES, SYSTEMS (0.1Hz-110GHz, nV-kV, fA-kA, pW-kW, UV-IR) * MATHEMATICS / MODELING, ANALYSES AND ... - 2019 Feb 01
Engineer Design
Bradford West Gwillimbury, ON, Canada
... for video pipelines and deep learning architecture design.Framebuf,GPU graphics driver OPENCV,openGL, CUDA,caffee and googlenet model AI/Machine learning algorith verification for face identification algorithm verification on xilinux fpga. ... - 2019 Jan 28
... for video pipelines and deep learning architecture design.Framebuf,GPU graphics driver OPENCV,openGL, CUDA,caffee and googlenet model AI/Machine learning algorith verification for face identification algorithm verification on xilinux fpga. ... - 2019 Jan 28
Computer Engineering Electrical
Toronto, ON, Canada
... Digital system final project Team Leader September 2018 – December 2018 A game named "Stack" was designed to be running on FPGA. We used a PS2 keyboard as our input and a VGA monitor and 7-segment display as output. The code were written in Verilog, ... - 2019 Jan 20
... Digital system final project Team Leader September 2018 – December 2018 A game named "Stack" was designed to be running on FPGA. We used a PS2 keyboard as our input and a VGA monitor and 7-segment display as output. The code were written in Verilog, ... - 2019 Jan 20
Software Development, Electrical, Project Engineer EIT
Toronto, ON, Canada
... VHDL, Verilog: Simulated ALU in FPGA Board including pipelining. EMPro, IntelliSuite: Simulated Micro-chip. Designed and Simulated Electrostatic Comb Actuator. ADS, Cadence: Designed and Simulated Fully Differential Amplifier and Phase Locked Loop ... - 2018 Nov 18
... VHDL, Verilog: Simulated ALU in FPGA Board including pipelining. EMPro, IntelliSuite: Simulated Micro-chip. Designed and Simulated Electrostatic Comb Actuator. ADS, Cadence: Designed and Simulated Fully Differential Amplifier and Phase Locked Loop ... - 2018 Nov 18
Engineer Microsoft Office
Toronto, ON, Canada
... Skills and Highlights • Software Programming skills: C, C++, Linux Kernel and Driver, Debian Ubuntu (UNIX), Shell Scripting, MATLAB, Python, Yocto Project, GNU toolchain, Assembly, Multisim, Eclipse IDE, and Xilinx (FPGA/VHDL) • Hardware skills: ARM ... - 2018 Oct 22
... Skills and Highlights • Software Programming skills: C, C++, Linux Kernel and Driver, Debian Ubuntu (UNIX), Shell Scripting, MATLAB, Python, Yocto Project, GNU toolchain, Assembly, Multisim, Eclipse IDE, and Xilinx (FPGA/VHDL) • Hardware skills: ARM ... - 2018 Oct 22
Engineer Design
Woodbridge, ON, Canada
... - Verilog design for CPLD and FPGA; Electronic circuitry design skill - Used TI, Qualcomm, MTK, Freescale, microchip, Atmel, NXP, Allwinner CPU/MCU in design; - Understand the structure of Cortex-A, Cortex-M serial CPU, also familiar with PIC, AVR ... - 2018 Sep 10
... - Verilog design for CPLD and FPGA; Electronic circuitry design skill - Used TI, Qualcomm, MTK, Freescale, microchip, Atmel, NXP, Allwinner CPU/MCU in design; - Understand the structure of Cortex-A, Cortex-M serial CPU, also familiar with PIC, AVR ... - 2018 Sep 10
Design Engineering
Toronto, ON, Canada
... Roman Genov Fall 2016 Design and layout of Dual Slope ADC Design and Layout of 4-bit multiplier Design and Layout of Decoder for Optimum Performance FPGA Architecture Prof. Vaughn Betz Fall 2016 Pipelined and Resource Shared Quadratic Expression ... - 2018 Aug 31
... Roman Genov Fall 2016 Design and layout of Dual Slope ADC Design and Layout of 4-bit multiplier Design and Layout of Decoder for Optimum Performance FPGA Architecture Prof. Vaughn Betz Fall 2016 Pipelined and Resource Shared Quadratic Expression ... - 2018 Aug 31
Electronic Technician
Scarborough, ON, Canada
... Graduate Apprentice Engineer (R&D department) July 2016- Dec.2016 Indian Telephone Industries Limited, Bangalore, India VHDL coding and implementation for FPGA (XILINX/ALTERA) IP cores. Implementation and testing of IP cores on FPGA Evaluation kit ... - 2018 Jun 29
... Graduate Apprentice Engineer (R&D department) July 2016- Dec.2016 Indian Telephone Industries Limited, Bangalore, India VHDL coding and implementation for FPGA (XILINX/ALTERA) IP cores. Implementation and testing of IP cores on FPGA Evaluation kit ... - 2018 Jun 29
Electronic Engineer
Richmond Hill, ON, Canada
... Excellent knowledge in FPGA design with Verilog HDL, RTL, synthesis, simulation and timing analysis. Basic programming C for hardware and firmware test and debug. Very strength at troubleshooting, debug, analytical and problem-solving skills. ... - 2018 Mar 12
... Excellent knowledge in FPGA design with Verilog HDL, RTL, synthesis, simulation and timing analysis. Basic programming C for hardware and firmware test and debug. Very strength at troubleshooting, debug, analytical and problem-solving skills. ... - 2018 Mar 12