| Resume alert | Resumes 51 - 60 of 119 |
Design Project
New Delhi, DL, 110001, India
... SUMMARY:- Knowledge of FPGA Digital signal processing and Communication System Design and concept of DSP Tool used. Designing of digital Filter and good knowledge on up sampling, Interpolation, down sampling. Knowledge of FPGA Based AM Modulation ... - 2016 Feb 23
... SUMMARY:- Knowledge of FPGA Digital signal processing and Communication System Design and concept of DSP Tool used. Designing of digital Filter and good knowledge on up sampling, Interpolation, down sampling. Knowledge of FPGA Based AM Modulation ... - 2016 Feb 23
Electrical Design Engineer
New Delhi, DL, 110001, India
... Course: PG Certificate in VLSI Design I gained industrial insight into various technologies & tools like Digital system, FPGA design flow from RTL design to programming device using Xilinx Tool Expertise in Synthesis, Place & Rout, Static Timing ... - 2016 Feb 10
... Course: PG Certificate in VLSI Design I gained industrial insight into various technologies & tools like Digital system, FPGA design flow from RTL design to programming device using Xilinx Tool Expertise in Synthesis, Place & Rout, Static Timing ... - 2016 Feb 10
Project Engineer
New Delhi, DL, 110001, India
... o From this we can monitor via wireless sensor network o Language of implementation : mat lab,Embedded Minor 5- Implemented on FPGA (Spartan 3E) o Word scrolling on 7-segment display o Keyboard interfacing o FIFO o Digital clock - 2016 Feb 08
... o From this we can monitor via wireless sensor network o Language of implementation : mat lab,Embedded Minor 5- Implemented on FPGA (Spartan 3E) o Word scrolling on 7-segment display o Keyboard interfacing o FIFO o Digital clock - 2016 Feb 08
Engineer Project
Gurgaon, HR, 122001, India
... Noida from December 2013 to September 2014 RTL Designing using Verilog & VHDL Verification using System Verilog in VMM Worked on Basic Protocols – I2C, UART, Arbiter Design System Explored RTL development techniques Worked on FPGA (Digilent Spartan ... - 2016 Feb 02
... Noida from December 2013 to September 2014 RTL Designing using Verilog & VHDL Verification using System Verilog in VMM Worked on Basic Protocols – I2C, UART, Arbiter Design System Explored RTL development techniques Worked on FPGA (Digilent Spartan ... - 2016 Feb 02
Engineering Power
Dadri, UP, 203207, India
... VI Feature Vector Extraction for a chronic seizure detection 5 months FPGA Languages and Software used: Verilog, MATLAB A Verilog design using gates and logic is designed for extracting the feature vector for detection of chronic seizures. And then ... - 2016 Jan 17
... VI Feature Vector Extraction for a chronic seizure detection 5 months FPGA Languages and Software used: Verilog, MATLAB A Verilog design using gates and logic is designed for extracting the feature vector for detection of chronic seizures. And then ... - 2016 Jan 17
Engineering Design
New Delhi, DL, 110001, India
... Tanner EDA (Schematic Editor, TSPICE, L-Edit } • Hardware Programming Languages: VHDL, RTL Design with Verilog, System Verilog, FPGA Prototyping • Scripting languages: Perl, Shell, Linux and MYSQL ACADEMIC BACKGROUND • GATE-2015 Qualified • M. ... - 2016 Jan 11
... Tanner EDA (Schematic Editor, TSPICE, L-Edit } • Hardware Programming Languages: VHDL, RTL Design with Verilog, System Verilog, FPGA Prototyping • Scripting languages: Perl, Shell, Linux and MYSQL ACADEMIC BACKGROUND • GATE-2015 Qualified • M. ... - 2016 Jan 11
Engineer Project
New Delhi, DL, India
... Mentor Graphics QuestaSim GRAM CORPORATION June 2012 to till April 2013 ABOUT COMPANY Gram Corporation specializes in VLSI ASIC, FPGA and Verification services. Gram Corporation is a leading offshore software & Hardware development company with ... - 2015 Dec 10
... Mentor Graphics QuestaSim GRAM CORPORATION June 2012 to till April 2013 ABOUT COMPANY Gram Corporation specializes in VLSI ASIC, FPGA and Verification services. Gram Corporation is a leading offshore software & Hardware development company with ... - 2015 Dec 10
Trainees
Gurgaon, HR, India
... Design and implementation of UART using FPGA-ALTERA DE1. Implementation of audio player using IC2 protocol in VERILOG. C,C++,Java, Ms-Office, Internet Usage, Arduino IDE, Eagle,Proteus. Orcad 7. Have a competitive attitude and can thrive under ... - 2015 Nov 13
... Design and implementation of UART using FPGA-ALTERA DE1. Implementation of audio player using IC2 protocol in VERILOG. C,C++,Java, Ms-Office, Internet Usage, Arduino IDE, Eagle,Proteus. Orcad 7. Have a competitive attitude and can thrive under ... - 2015 Nov 13
Design Engineer
Faridabad, HR, India
... Xilinx ISE & System Ed., Cadence - NCSim, RTL compiler, SoC Encounter, Virtuoso, Synopsys- TCAD Hardware Platform Xilinx FPGA Spartan 3AN, Digilent Nexys3 Spartan6 Others Makefiles, Vi Editor, gedit, Microsoft Office QA Skills Manual (SIL) Testing ... - 2015 Nov 12
... Xilinx ISE & System Ed., Cadence - NCSim, RTL compiler, SoC Encounter, Virtuoso, Synopsys- TCAD Hardware Platform Xilinx FPGA Spartan 3AN, Digilent Nexys3 Spartan6 Others Makefiles, Vi Editor, gedit, Microsoft Office QA Skills Manual (SIL) Testing ... - 2015 Nov 12
Design Engineering
New Delhi, DL, India
... Basic Knowledge of FPGA and Mentor Graphics tool. EXTRA CO-CURRICULAR ACTIVITIES Participated in College Level Quiz. First and Third prize in Dance competitions at Sangrur Kala Kendra. DECLARATION I hereby declare that the above mentioned ... - 2015 Oct 30
... Basic Knowledge of FPGA and Mentor Graphics tool. EXTRA CO-CURRICULAR ACTIVITIES Participated in College Level Quiz. First and Third prize in Dance competitions at Sangrur Kala Kendra. DECLARATION I hereby declare that the above mentioned ... - 2015 Oct 30