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Pooja Chaudhary

acs2cd@r.postjobfree.com

POOJA CHAUDHARY

M.TECH VLSI DESIGN

CAREER OBJECTIVE

To pursue a challenging career and be part of a progressive organization that gives scope to enhance my knowledge, skills and to reach the pinnacle in the computing and research field with sheer determination, dedication and hard work.

TECHNICAL PROFICIENCY

• Software Programming Language: C,C++,Assembly Language 8051

• Operating Systems: Windows XP, Linux version 5.4 and 6.0

• HDL Simulators: Mentor Graphics ModelSim SE v6.0a

• Circuit Simulators: Cadence {RTL Compiler, SOC Encounter, Layout Editor (Virtuoso Specter), Assura, gpdk upto 45nm), LTSPICE, Tanner EDA (Schematic Editor, TSPICE, L-Edit }

• Hardware Programming Languages: VHDL, RTL Design with Verilog, System Verilog, FPGA Prototyping

• Scripting languages: Perl, Shell, Linux and MYSQL ACADEMIC BACKGROUND

• GATE-2015 Qualified

• M. Tech (VLSI Design) from ITM University, Gurgaon in year 2014 with 7.67 CGPA

• B. Tech (ECE) from Amity University, Noida in year 2012 with 7.43 CGPA

• Senior secondary from CBSE, in year 2007

• Secondary from CBSE, in year 2005

WORKING EXPERIENCE

• Currently working as a visiting faculty in Electronics and Communication Engineering Department at Amity University.

RESEARCH PAPER PUBLISHED

“Estimation of Logic Efforts for a Three-Stage Decoder using NAND Logic at 0.35µm Technology” Published in National Conference on Contemporary Techniques & Technologies in Electronics Engineering March 2013

PooP

Pooja Chaudhary

acs2cd@r.postjobfree.com

“Power Analysis of CMOS Combinational Logic Circuits using Adiabatic Reduction Technique at 180nm Technology” Published in International Journal of Engineering Research and Applications

(IJERA) Volume -3, Issue-6, December 2013 Publication. [ISSN: 2248 -9622 Online]

“Design and Power Analysis of Sequential Circuits using Adiabatic Technique” Published in International Journal of Enhanced Research in Science Technology and Engineering (IJERSTE) Volume -3, Issue-3, March 2014 Publication.

“Design of Low Power Memory Cell Using D Flip Flop Under Adiabatic Reduction Technique

” Accepted to International conference on Signal Processing and Integrated Networks (SPIN)-2016

“Optimization of Area and Delay in Low-Power Memory Cell Through Adiabatic Technique”

(Soon to be published)

PROJECT WORK/ TECHNICAL EXPERTISE

• Successfully completed work on “Design of Low-Power Memory Cell Using D Flip-Flop Through Adiabatic Technique” using Cadence Virtuoso Tool May,2014

• Successfully completed work on “Design of Low Power CMOS Sequential Circuits Using Adiabatic Reduction Technique” using Cadence Virtuoso Tool December,2013

• Successfully designed a project on “Attendance Management using Scripting” July, 2013

• Successfully completed work on “Display of HELLO WORLD” on LCD using “FPGA interfacing” April, 2013

• Successfully completed work on “Designing of a CMOS Differential Amplifier” using Transistors on Cadence Virtuoso Tool March, 2013

• Analysis and Designing of “Digital Circuit Gate Sizing of a three stage Decoder using NAND gate guided by logical effort” on IC Design Flow (Mentor Graphic) Jan-April, 2012 TRANING ASSOCIATION AND WORKSHOP ATTENDED

• Summer Training in RedHat Enterprise Linux, Shell Scripting and Perl at Fostering Linux, Gurgaon

• Workshop on Linux and Python organized by IIT- Bombay at ITM University, Gurgaon PERSONAL DETAILS

Date of Birth: 16-05-1989

Father’s Name: Mr. Satish Chaudhary

Mother’s Name: Mrs. Sharda Chaudhary

PooP

Pooja Chaudhary

acs2cd@r.postjobfree.com

Linguistic Proficiency: Hindi, English

E-mail id: acs2cd@r.postjobfree.com

REFERENCES

1. Name: Dr. Anu Mehra Contact No- 981-***-****

Designation: Associate Professor E-mail: acs2cd@r.postjobfree.com Firm Details: AMITY University, Noida

2. Name: Dr. Neeraj Kr. Shukla Contact No- 921-***-**** Designation: Associate Professor E-mail: acs2cd@r.postjobfree.com Firm Details: ITM University, Gurgaon

3. Name: Parikshit Sirohi Contact No- 91-981******* Designation: Assistant Professor E-mail: acs2cd@r.postjobfree.com Firm Details: Delhi University, Delhi

DECLARATION

I hereby declare that the information furnished above is true to best of my knowledge. Place: Gurgaon

(POOJA CHAUDHARY)

Date: 05-01-2016

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