Engineer Project

CAREER OBJECTIVE

Willing to accept the challenges in an organization with challenging, diverse and dynamic job with

good amount of freedom and work responsibility.

SUMMARY

3.0 year of experience in ASIC Design and Verification.

Area of Expertise: Functional Verification, Digital Design and RTL Coding.

Proficient in design using Verilog HDL, VHDL.

Proficient in verification using System Verilog UVM.

Protocols AMBA AXI, I2C, SPI.

Tools used ModelSim, Questa Sim, Xilinx ISE, Altera Quartus, Active HDL, & PSPICE.

PROFESSIONAL EXPERIENCE

CETPA InfoTech Pvt. Ltd. April 2013 to till the date

ABOUT COMPANY

CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.

DESIGANATION: VLSI Engineer

Project1: Verification of SPI Master Slave core using Wishbone

Brief Description: The test bench architecture is based on the Universal Verification Methodology (UVM) which enables the creation of highly reusable and scalable test benches. In the project WB SPI verification validates the parallel to serial transfer by writing to the registers during read and writes transactions

Tools & Environment:

System Verilog (UVM) test bench environment, with scoreboards, monitors, environment, driver, DUT & top test bench file.

Mentor Graphics QuestaSim.

Project 2:Verification of FIFO using System Verilog (UVM)

Brief Description: The Synchronous FIFO is a First-In-First-Out memory queue with control logic that manages the read and writes pointers, generates status flags, and provides optional handshake signals for interfacing with the user logic.

Tools & Environment:

UVM test bench environment with UVM sequence, UVM component modeling, agent modeling & scoreboard modeling.

Mentor Graphics QuestaSim.

Project 3:Verification of Vending Machine controller using System Verilog (UVM)

Brief Description: The vending machine controller is a device which gives outputs on the basic of its different inputs. In the UVM test bench environment I have written transactions, driver, monitor and scoreboard also.

Tools & Environment:

UVM test bench environment with UVM sequence, UVM component modeling, agent modeling & scoreboard modeling.

Mentor Graphics QuestaSim.

Project 4:Verification of RAM using System Verilog

Brief Description: In this project there are simple memories in which it has some data input & output port, address port and read and write enable pins. I have created a complete system Verilog based test bench environment in which I have designed test cases, driver, monitor and scoreboard.

Tools & Environment:

System Verilog test bench environment

Mentor Graphics QuestaSim.

Project5: Designing of I2C protocol

Brief Description: The I2C Controller Bus is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. I2C provides good support for communication with various slow, on-board peripheral devices that are accessed intermittently while being extremely modest in its hardware resource needs. It is a simple, low-bandwidth, short-distance protocol.

Tools & Environment:

A complete System Verilog test bench environment.

Mentor Graphics QuestaSim on Windows, ModelSim, Xilinx ISE 14.1

Project6: Verification of UART using System Verilog

Brief Description: A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with Programming that controls a computer's interface to its attached serial devices. Specifically, it provides the computer with the RS-232C Data Terminal Equipment (DTE) interface so that it can "talk" to and exchange data with modems and other serial devices.

Tools & Environment:

System Verilog test bench environment, with scoreboards, monitors & generator for Transmitter and receiver.

Mentor Graphics QuestaSim

GRAM CORPORATION June 2012 to till April 2013

ABOUT COMPANY

Gram Corporation specializes in VLSI ASIC, FPGA and Verification services. Gram Corporation is a leading offshore software & Hardware development company with specialization in the areas of Electronics since 2004 in Delhi.

DESIGANATION : Design Engineer

Project 7 : Design of UART using Verilog HDL

Brief Description: The HD 6402 is a UART for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. Utilizing the intersil advanced scaled CMOS process permits operation clock frequencies up to 8MHz (500k baud). Power requirement by comparison, are reduced from 300mV to 10mV.

Tools & Environment: ModelSim, Xilinx ISE, VHDL/Verilog HDL.

Project 8: Design of 8 bit RISC Processor Verilog HDL

Brief Description: Processor is design to support 16 instructions with three addressing modes. Two-stage pipelining is used to execute one instruction per cycle and 12-bit instruction format to decode instructions. 16 internal registers are used to speed up register-to-register operations and only Simple LOAD and STORE operations accessing memory. This design implemented on Xilinx Spartan3.

Tools & Environment: ModelSim, Xilinx ISE, Verilog HDL, Spartan 3E

SEMINARS & WORSHOPS

Workshop on FPGA/CPLD Implementation of Verilog/VHDL Code to IRDE (A subsidiary of DRDO) in Dehradun.

Delivered seminar on VLSI Front End Designing on DIT University, Dehradun.

TECHINICAL SKILLS

HDL/HVL : VHDL,Verilog HDL,System Verilog

Verification Methodology: System Verilog UVM

Simulator: Model Sim 6.5 & 10.0, Questa Sim 10.0, Active HDL 8.1

Synthesis Tool: Xilinx ISE 14.1, Altera Quartus

Backend Design Tool : PSpice

Programming Language: C, C++.

Scripting Language: Perl (Introductory), MATLAB

Operating System: Microsoft Windows,Linux

Hardware Implementation : FPGA & CPLD

ACADEMIA

Advance diploma in VLSI Technology from DUCAT India Pvt. Ltd.

B.Tech (Electronics & Communication Engineering) from SIET, Gr.Noida with aggregate 73% of marks in 2012.

12th (Science) from UP Board with 74% of marks.

10th (Science) from UP Board with 68% of marks.

INDUSTRIAL TRAINING

1. Industrial Training in NTPC, Tanda (U.P.)

Department: Control & Instrumentation Department

Duration : One and half month From June-11 to July-11

2. Advance diploma in VLSI Front End Designing & Verification (VHDL/Verilog HDL/System Verilog)

Diploma in Front end designing & verification from DUCAT, Noida

Duration: Six Month from August-11 to January -12

STRENGTH

Extremely energetic, hard working determined and challenge loving, self motivated, Committed to excellence, Good communication & Interpersonal skill, Quick Learner. Lateral Thinking, Open to new Experience.

PERSONAL DOSSIER

Father’s name Mr. Jitendra Kumar Shriwastava

Date of Birth 2 nd April, 1990.

Linguistic Abilities English & Hindi.

DECLERATION

I hereby declare that the above furnished information is correct to the best of my knowledge & belief.

Place: Delhi Piyush Shriwastava

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