Design Engineer

* * ******.**********@*****.***

ASHIMA GANDHI

H.No. 647, Sector - 15/A

Faridabad - 121007 (Haryana) India

E-mail: ******.**********@*****.***

Contact: +91-981*******, +91-956*******

https://in.linkedin.com/pub/ashima-gandhi/47/93/648 OBJECTIVE

Looking forward to be a part of the Research and Development team where I can learn and grow my technical and professional skills

CURRENT OBJECTIVE

To be a part of research and project team as an Intern for Six Months (Dec’15/ Jan’16 - May’16/ Jun’16) duration in VLSI Design

PROFESSIONAL SYNOPSIS

1.5 months of training experience in Functional Verification using SystemVerilog in Mentor Graphics, Bangalore as an intern

1.3 years of Industrial experience in Software Testing in Automotive Embedded System domain in Magneti Marelli UM Electronic Systems Pvt Ltd (A FIAT Group. Company) as Testing Engineer -R&D

Working Experience on SIL(Software-in-the-Loop) Testing, on IBM Rational Team Concert, Telelogic DOORS, MxVDev Tool (from MicroMax), Visual C++ 2008 Express Edition

Worked in different phases of STLC as Study & Understand the Requirements, Preparation of Test Plan, Test Scenarios, Test procedures, Test Cases, Execution of Test Cases and Defect Reporting & Tracking etc

Roles and Responsibilities: Customer Requirement analysis, Documentation, SIL Testing, Integration Testing, Regression Testing, Test Specification Prepare, Review activities, Query/Report management and Planning, Task creation in RTC, creating software virtual for execution of the VFs, conducting project specific and tool usage knowledge sessions to new comers, managing Daily activity tracker of the team. ACADEMIC CREDENTIALS

Qualification Institution Year Board /University Percentage/ Grades of Marks

M.Tech

(VLSI Design)

ITM University,

Gurgaon (Haryana)

India

Pursuing ITM University, Gurgaon

(Haryana) India

7.81/10

(upto 2nd Semester)

B.Tech

(Electronics &

Communication)

Lingaya’s Institute

of Management

and Technology,

Faridabad

(Haryana)

2012

Maharishi Dayanand

University, Rohtak

(Haryana) India

71%

Senior Secondary Kendriya Vidyalaya

No.2, Faridabad

2008

Central Board Of

Secondary Education

(CBSE)

72.4%

Secondary Kendriya Vidyalaya

No.2, Faridabad

2006

Central Board of

Secondary Education

(CBSE)

84.2%

2 4 ******.**********@*****.***

TECHNICAL SKILLS

Software Languages C, C++ (OOPs Basics)

Operating Systems Windows, Linux

Hardware Languages

(HDL & HVL)

Verilog HDL, SystemVerilog

EDA & Simulation

Software

Questa Sim10.0b, Xilinx ISE & System Ed., Cadence - NCSim, RTL compiler, SoC Encounter, Virtuoso, Synopsys- TCAD

Hardware Platform Xilinx FPGA Spartan 3AN, Digilent Nexys3 Spartan6 Others Makefiles, Vi Editor, gedit, Microsoft Office QA Skills Manual (SIL) Testing, Verification & Validation, Design and Documentation, Test case implementation and Execution, Bug Discovery and Documentation, Regression Testing, Requirement Analysis, Test Case Creation

Protocols used Controller Area Network (CAN), Local Area Network (LAN) Editors and Defect

Tracking Tools

Visual C++ 2008 Express Edition

IBM - Rational Team Concert

COURSES

SystemVerilog for Verification,

Digital System Design with VerilogHDL,

Design & Analysis of Computer Architecture,

Computer Aided VLSI Design,

Embedded System Design,

VLSI Fabrication and Technology

PUBLICATIONS

A Survey on Power Reduction Techniques in SRAM Cells …to be communicated In this paper, a broad survey of power reduction methods for different kind of SRAM cells utilized in memory is done and the design parameter power is calculated keeping in mind the power-area and power-delay trade- offs. Different SRAM cells (6T, 7T, 8T, 9T and 10T) are analyzed on different technologies (45 nm, 60 nm, 65nm, 90 nm, 180 nm) in terms of power, area, speed, reliability, stability and delays. PROJECTS

LC3 processor Verification

Summary: Verified the functionality of an LC3 processor using SystemVerilog layered testbench. Programmed the driver, generator, scoreboard, interface, receiver and checker blocks of the testbench for the individual fetch, decode, execute, writeback and controller modules of the LC3 processor. The completely integrated LC3 processor was also verified using a testbench that incorporated Golden Reference Models and assertions. This test bench was fully modular and reusable having used object oriented programming concepts. QuestaSim simulator was used in simulating this design and also in achieving 100% functional coverage, to ensure complete verification.

Employed LCR-SRAM scheme to reduce leakage power in SRAM cells Summary:

SRAM is a key component of the processing system of sensor nodes and has to satisfy the low power requirement for sensing, processing and communication. In this project Leakage Current Reduced SRAM was used which reduced the leakage power dissipation significantly in comparison to the conventional 6T- 3 4 ******.**********@*****.***

SRAM cell. The cell designing and simulation was done using GPDK-90 nm technology library under Cadence Virtuoso design environment. The proposed cell scheme uses a lower voltage than Vdd during standby mode which leads to a reduction of leakage current and hence the static power consumption. The lower voltage is generated using an NMOS which creates a threshold voltage drop when transfer a high logic. The power consumption was found to be 25.02 % lesser than that of conventional six transistors SRAM cell.

RTL to GDSII conversion of Arithmetic Logic Unit using RTL Compiler and Cadence SoC Encounter Summary:

16-bit ALU code is simulated on Xilinx ISE Simulator and synthesized using RTL compiler . Then GDS II is extracted from the netlist obtained using RTL compiler using Encounter. GDS II is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork.

FPGA prototyping of Automatic Newspaper Vending Machine using VerilogHDL Summary:

Implementation of Automatic Newspaper Vending Machine using Finite State Machine (FSM) methodology in VerilogHDL done on Spartan 3AN.

Hardware and Software: FPGA, Xilinx ISE, VerilogHDL

Design of various device structures and their processes using Synopsys TCAD Summary:

Using TCAD a process sequence to fabricate the twin-tub CMOS structure, Integrated Resistor and Integrated Capacitor are designed. Sentarurus structure editor, process, structure device, structure workbench, structure mesh, Svisual are used.

Industrial Projects:

Project Title : S20 (IVECO Trucks), 343HB (Viaggio hatch back cars), P521(FIAT cars) – Autosar Project Organization: Magneti Marelli (FIAT Group.)

Environment : IBM Rational Team Concert, Telelogic DOORS, MxVDev Tool, Visual C++ 2008 Studio Duration : 1.3 years

Team size : 10

Skills : CAN, C-Programming

Client : FIAT

Project Responsibilities

Analysis of the customer requirements mentioned in System Requirements in DOORS

Discussion of requirements with architect of the concerned Vehicle Function

Creating design document from the system requirements of the VF

Creating Module under Test using Visual C++ 2008 Studio

Creating Test Plan and Report (test scenarios and test cases) from the requirements

Test case design using MxVDev Micromax tool

Test case Execution (SIL Testing, Integration Testing, Regression Testing)

Raising bugs in Bug reporting tool i.e Rational Team Concert

Defect Resolving through minor changes in code

Defect Management

Discussion of defects with architects and software reference TRAINING & INTERNSHIP

Six weeks training in “Verification using SystemVerilog” at Mentor Graphics India Pvt Ltd, Bangalore in June-July 2015.

Six weeks training in “Designing using VerilogHDL” at 3ST Technologies, Noida in Dec-Jan 2015

Four weeks internship at Avery India Pvt Ltd, Faridabad in June - July 2011 4 4 ******.**********@*****.***

WORKSHOPS ATTENDED

Attended two days workshop on TCAD in Udaipur, Rajasthan

Attended National workshop organized by ITM University on MEMS Technology

Attended various presentations and workshops on latest Automotive Technology ABOUT MYSELF

Good knowledge and experience on Verification and Validation

Dedicated and highly ambitious to achieve personal as well as organizational goals

Keen learner with ability to learn & imbibe new knowledge with ease

Honest, Hard Working, Team Player Spirit

Committed to the tasks undertaken, Learning and Working Approach REFERENCES

1. Dr. Neeraj Kr. Shukla

Associate Professor-Department of EECE

Project Manager-VLSI Design

ITM University, HUDA Sector-23A,

Gurgaon-122017 (Haryana) India

E-mail: *************@********.***

Contact: +91-921*******

2. Dr. Preetham Lakshmikanthan

Design Engineer/Front end Lead Trainer

RV-VLSI Design Center, Bangalore

Karnataka, India

Email: ********.*******@*****.***

Contact: 096********

3. Mr. Dinesh Kumar

Head Operations/Plant Manager

Magneti Marelli Powertrain India Pvt Ltd

Plot No 1, Subplot No 22 & 25,

Manesar, Gurgaon – 122051 (Haryana) India

E-mail: ******.*****@**************.***

Contact: +91-931*******

4. Mr. Aseem Batra

Technical Leader

STMicroelectronics Pvt Ltd

Greater Noida, Plot No.1, Knowledge Park III, India Email: *****.*****@**.***

Contact: +91-991*******

DECLARATION

I declare that the information given above is true and correct to the best of my knowledge. Place: Faridabad (Haryana)

Date: ASHIMA GANDHI

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