| Resume alert | Resumes 21 - 30 of 182 |
Student at University of Southern California
Los Angeles, CA
... Artix -7 FPGA Nexys4 Board, Innovus(Automated Place and Route), NCSIM,Design Compiler, Others: GPGPU: SIMT- Stack, Score Board, Task Manager, I-Buffer, Operand Collector Protocols: PCIe, PCI, AXI, MOESI, ACK/NAK, DDR Memory technologies: DDR (I, II, ... - 2020 Oct 22
... Artix -7 FPGA Nexys4 Board, Innovus(Automated Place and Route), NCSIM,Design Compiler, Others: GPGPU: SIMT- Stack, Score Board, Task Manager, I-Buffer, Operand Collector Protocols: PCIe, PCI, AXI, MOESI, ACK/NAK, DDR Memory technologies: DDR (I, II, ... - 2020 Oct 22
Python Manager
Fullerton, CA
... internal ERP system • Worked with SRM provider Jaggaer to enable internal and external suppliers onto UCSD P2P platform PROJECTS FPGA-GPU Research Paper 2/2020 – Current • Working on a research paper with the Pattern Recognition Lab comparing the ... - 2020 Oct 10
... internal ERP system • Worked with SRM provider Jaggaer to enable internal and external suppliers onto UCSD P2P platform PROJECTS FPGA-GPU Research Paper 2/2020 – Current • Working on a research paper with the Pattern Recognition Lab comparing the ... - 2020 Oct 10
Electrical Engineer Design
Fullerton, CA
... SKILLS • Signal Processing MATLAB • PCB Circuit Design Altium Designer, Kicad • Microsoft Office • Electronic Circuit Analysis PSPICE, Proteus • Robot Operating System (ROS) • Microcontroller AVR, ARM • FPGA Verilog • AutoCAD • SolidWorks • Fusion • ... - 2020 Sep 15
... SKILLS • Signal Processing MATLAB • PCB Circuit Design Altium Designer, Kicad • Microsoft Office • Electronic Circuit Analysis PSPICE, Proteus • Robot Operating System (ROS) • Microcontroller AVR, ARM • FPGA Verilog • AutoCAD • SolidWorks • Fusion • ... - 2020 Sep 15
Electrical Engineer Design
Los Angeles, CA
... Education: Illinois Institute of Technology, Chicago, IL Aug 2016 - May 2018 • Master of Science Electrical Engineering (M.S.E.E.) Major GPA 3.8 Majored in VLSI and Microelectronics with a focus on CMOS circuit design, FPGA, SoC and RTL development ... - 2020 Aug 10
... Education: Illinois Institute of Technology, Chicago, IL Aug 2016 - May 2018 • Master of Science Electrical Engineering (M.S.E.E.) Major GPA 3.8 Majored in VLSI and Microelectronics with a focus on CMOS circuit design, FPGA, SoC and RTL development ... - 2020 Aug 10
Fourth-Year studying B.S. Computer Engineering
Diamond Bar, CA, 91765
... Developed and programmed circuits with PIC18F and C or PIC18F assembly Collaborated with other students FPGA Arithmetic Microcontroller Laboratory Student Jan 2019 - May 2019 Implemented circuit design using Verilog and FPGA Programmed, simulated, ... - 2020 Jul 16
... Developed and programmed circuits with PIC18F and C or PIC18F assembly Collaborated with other students FPGA Arithmetic Microcontroller Laboratory Student Jan 2019 - May 2019 Implemented circuit design using Verilog and FPGA Programmed, simulated, ... - 2020 Jul 16
Design Engineer Engineering
Los Angeles, CA
... Education: Master of Science in Electrical and Computer Engineering, Dec 2019 California State University, Northridge (GPA 3.3/4) Courses: FPGA, System on Chip (SOC), Computer Architecture, Advanced Switching Theory, Digital System Auto VHDL, ... - 2020 Jul 13
... Education: Master of Science in Electrical and Computer Engineering, Dec 2019 California State University, Northridge (GPA 3.3/4) Courses: FPGA, System on Chip (SOC), Computer Architecture, Advanced Switching Theory, Digital System Auto VHDL, ... - 2020 Jul 13
Software Developer Engineer
Van Nuys, CA
... Logic, Machine Learning, and FPGA design • Department and University honors • Overall GPA: 3.53 PROJECTS • Parking lot counter written in C++: Visual display of individual open and occupied parking spaces and how many spaces are open and occupied. ... - 2020 Jul 05
... Logic, Machine Learning, and FPGA design • Department and University honors • Overall GPA: 3.53 PROJECTS • Parking lot counter written in C++: Visual display of individual open and occupied parking spaces and how many spaces are open and occupied. ... - 2020 Jul 05
Engineering Computer
Buena Park, CA
... (VHDL), EGCP 441: Advanced Electronics for Computer Engineers, EGCP 446: Advanced Digital Design Using Verilog HDL (FPGA Programming), EGCP 447: Introduction to Hardware Security, EGCP 450: Embedded Processor Interfacing, EGCP 461: Low Power ... - 2020 May 30
... (VHDL), EGCP 441: Advanced Electronics for Computer Engineers, EGCP 446: Advanced Digital Design Using Verilog HDL (FPGA Programming), EGCP 447: Introduction to Hardware Security, EGCP 450: Embedded Processor Interfacing, EGCP 461: Low Power ... - 2020 May 30
Mechanical Engineering
Woodland Hills, CA
... Learned about the theory of Fourier transforms and programming a Field Programmable Gate Array (FPGA). Presented group work to school faculty and working professionals in industry. Relevant Skills ●Punctual, diligent, and highly responsible. ... - 2020 May 26
... Learned about the theory of Fourier transforms and programming a Field Programmable Gate Array (FPGA). Presented group work to school faculty and working professionals in industry. Relevant Skills ●Punctual, diligent, and highly responsible. ... - 2020 May 26
Food Safety Digital Marketing
Fullerton, CA
... Electromagnetics in Communication, Introduction to Robotics, Numerical Analysis, Design Applications with Microcontroller and FPGA, Microprocessors and Systems Applications, Audio Video Engineering, Signals and Systems, Data Structures & algorithm. ... - 2020 May 14
... Electromagnetics in Communication, Introduction to Robotics, Numerical Analysis, Design Applications with Microcontroller and FPGA, Microprocessors and Systems Applications, Audio Video Engineering, Signals and Systems, Data Structures & algorithm. ... - 2020 May 14