PRASHANT SAXENA

adg8as@r.postjobfree.com Los Angeles, CA 213-***-**** https://www.linkedin.com/in/prashant-saxena-31b471128/ EDUCATION

University of Southern California, Los Angeles, California May 2021 Master of Science in Electrical Engineering, GPA 3.65/4.0 Coursework: Digital System Design (EE560), VLSI System Design (EE577B), Computing Principles for Electrical Engineers (C++)

(EE599), VLSI System Design (EE577A), Computer Systems Architecture (EE557), Computer Systems Organization (EE457), MOS VLSI Circuit Design (EE477)

Certified Courses: 1. VSD Physical Design Flow: Floor Planning, Placement and Route, STA, clock tree Synthesis, DRC 2. SOC Verification using System Verilog

SRM Institute Of Science and Technology, Chennai, India (First Class with Distinction) May 2018 Bachelor Of technology in Electronics and Communication Engineering (ECE), CGPA: 9.51/10 SKILLS

Programming skills: Verilog, VHDL, SystemVerilog, SystemVerilog Assertions and Functional coverage, Python, C++, Data structures and Algorithms

Tools/Packages: Vivado, Adept, HSPICE, ModelSim, QuestaSim, Xilinx ISE, Cadence Virtuoso, Computer simulation Technology

(CST), PSPICE simulation software, LabVIEW, Oracle VM Virtual Box, MS Office. Artix -7 FPGA Nexys4 Board, Innovus(Automated Place and Route), NCSIM,Design Compiler, Others: GPGPU: SIMT- Stack, Score Board, Task Manager, I-Buffer, Operand Collector Protocols: PCIe, PCI, AXI, MOESI, ACK/NAK, DDR

Memory technologies: DDR (I, II, III, IV) SDRAM, DRAM RELEVANT WORK EXPERIENCE

Trainee, Bharat Electronics Limited (BEL), UP, India May 2018 - November 2018

• Trained in the field of Digital System design with FPGA using VHDL. VLSI intern, SION SEMICONDUCTORS, Bangalore, India December 2017 – January 2018

• Underwent Verilog HDL training under SOC verification. ACADEMIC PROJECTS

Peripheral Component Interconnect Express (PCIe) protocol implementation July 2020

• Implemented the PCIe’s Physical Layer Design having a 2-lane link.

• Implemented Elastic Buffer, Deskew Fifo, 8b/10 encoder and decoder,Simulated and synthesized the complete design using Vivado and instantiated ILA cores to debug the design by utilizing VIVADO Chipscope and observed the addition and deletion of skips (of the SOS: Skip ordered set).

• Tools and technologies used: Vivado, Chipscope, Verilog, Artix -7 FPGA Nexys4 Board In-Order-Issue, Out-of-Order Execution, In-Oder-Commitment Tomasulo based CPU Design July 2020

• Used VHDL for RTL designing of following components: Store buffer, Store address buffer, Free register list, Issue unit, Reorder Buffer (ROB), Dispatch unit and Performed Speculative execution beyond branch by designing branch prediction buffer.

• Implemented BRAM based Copy free Checkpointing (CFC) acting as FRAT. RRAT implemented using BRAM and ran multiple instruction streams (on Modelsim), synthesized on FPGA using Vivado and used Chipscope to debug.

• Tools and technologies used: ModelSim, Vivado, Chipscope, VHDL, Artix -7 FPGA Nexys4 Board Implementation of ARM’s Advanced eXtensible Interface (AXI) interconnect for SOC July 2020

• Designed AXI master and slave interfaces with Reorder buffers, read counters, packetization FIFO as key components in Verilog and designed 4 masters & 4 slaves with a 2*4 Mesh network as the Router interconnection network. Parallel Matrix multiplication on a Multi core Multi-threaded Processor (CMP) July 2020

• Used assembly language to perform parallel multiplication on the 16 threads of a 4-core-4 threaded CMP.

• Obtained Mutual Exclusion using LL and SC by executing lock and lockless mechanisms & Implemented Cache coherency protocol to support write back Cache.

• Tools and languages used: Assembly language, Artix -7 FPGA Nexys4 Board, ModelSim General Purpose Graphical Processing Unit (GPGPU) July 2020

• Performed assembly language programming for GPGPU with 1 Streaming Multiprocessor and with 8 warps and 8 threads. Clock Domain Crossing using Flow through and Pipelined BRAM/SSRAM June 2020

• Designed RTL using VHDL for a 2 clock FIFO providing zero consumption latency by having a small reg based FIFO. Full Custom Layout of a 16- bit 5-stage General purpose CPU 45nm technology April -May 2020

• Designed the schematic and layout of a 5 stage 16-bit CPU that supports memory read write operation, logical, Arithmetic operations and MEMORY stage is a 512-bit SRAM whose control signals were derived using a pulse generating hardware.

• Used power and area optimization techniques: clock gating (in decode stage), Dynamic Logic, 3 stage 5-bit Multiplier used & Complier based NOOPS inserted; IF stage and decode section of ID stage carried out using Scripting (python).

• Tools, technologies and languages use: python, Spectre, Cadence Virtuoso. Automated Place and Route for a 2 clock FIFO and Round Robin Synthesis RTL design in Verilog September 2020

• Synthesized 2 clock FIFO and Round Robin designs, ran pre and post synthesis simulations and ran automated place-and- route. Simulated the design post place-and-route. Tools used: Innovus, NCSIM, Design Compiler, QuestaSim. Design and Layout of a Digital Neuron (Brain Cell) SPECTRE simulation December 2019

• Created a schematic and layout of a digital neuron and performed Spectre simulations.

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