DEEPAK ANAND RAVINDRAN *(GRADUATED May’**)

****, *** ***, ********* *****, Los Angeles, CA 90007 Phone: 213-***-**** email: acrbk3@r.postjobfree.com Linkedin profile: https://www.linkedin.com/in/deepakanandravindran

OBJECTIVE Seeking Full-time position in the fields of Digital ASIC RTL Design/Verification and Computer Architecture. I am result-oriented and an effective, dependable team player.

EDUCATION

University of Southern California, Los Angeles, CA May 2015 Master of Science, Electrical Engineering GPA: 3.40

Courses Taken: EE457: Computer Systems Organization, EE477L: MOS VLSI Circuit Design, EE533: Network Processor Design and Programming, EE577A: VLSI System Design, EE560: Digital System Design - Tools and Techniques, EE577B: VLSI System Design, EE658: Diagnosis and Design of Reliable Digital Systems(DFT), EE557: Computer Systems Architecture

National Institute of Technology, Trichy, India May 2011 Bachelor of Technology, Electronics and Communication Engineering (ECE) GPA 8.23/10

WORK EXPERIENCE

CDOT Alcatel-Lucent Research Center Chennai, India Digital and Power Embedded Systems Hardware Design Engineer July 2011–July 2013 I was involved in the schematics design, layout review, component selection, BoM creation, firmware board bring-up (through Trace32 and JTAG) and PCB testing/debugging of Digital and Power subsystems of WCDMA and WiMAX mini Basestations.I understood the operation and interfacing of various peripherals like DDR2/DDR3, NAND/ NOR Flash, Ethernet PHY, PoE,LDOs,DC-DC converters, RF frontend etc. with the SoC processor. I also acquired insights on popular inter-board interfaces like PCI, SPI, I2C, UART, MII etc. and lab equipment like digital oscilloscope. This role required me to interact with colleagues across teams/domains (like the firmware team,mechanical product design team and the component procurement team), and helped hone communication and people skills.

TECHNICAL SKILLS

Key Skills : Verilog, C, Perl, SystemC, VHDL, C++

Operating Systems : Windows, Unix/Linux, Mac

Packages : Synopsys Design Compiler, Cadence NCSsim/NC-Verilog, Synopsys TetraMAX ATPG, Synopsys PrimeTime, Cadence Encounter SoC Auto P&R, Modelsim, SimpleScalar simoutorder CPU performance simulator,Cadence Conformal LEC, Xilinx ISE/Chipscope, Cadence Virtuoso Schematics Editor/Layout Suite, Iperf, Mentor Graphics DxDesigner, Cadence OrCAD Capture, Altera Quartus II, Trace32 JTAG

PROJECTS

1) DDR2 Memory Controller at 2.6ns clock Design, Synthesis and Auto P&R Oct 2014- Dec 2014 Designed 2.6ns clock DDR2 Memory Controller ASIC from RTL to GDS2 - Verilog RTL, synthesis using Synopsys DC, Auto Place-and-Route using Cadence Encounter SoC. Timing was met using PrimeTime STA and post-layout simulation performed on the GDS II. The design implemented initialization engine and processing logic for issuing timed control signals for scalar, block and atomic(simple ALU ops) read/write operations, apart from refresh commands to the Denali IP Micron DDR2 Memory module.

2) D- Algorithm Combinational ATPG (C language) for compressed fault list Nov 2014- Dec 2014 D Algorithm was realized in C language for combinational circuits with reconvergent fanouts. The program reads the netlist from circuit file described in ISCAS-85 format and a preprocessor routine generates compressed fault list for circuit. D ATPG routine is then called to generate test vectors for compressed faults, for fault simulation.

3) RTL Design and Implementation of 32-bit CFC-based Tomasulo single-core processor in Xilinx Artix 7 FPGA July 2014 - Aug 2014 Designed 32-bit Tomasulo processor with a subset of MIPS32 ISA having IF stage with blocking cache, and 4-deep IFQ, 2-stage Dispatch unit with 8-deep BPB and 4-deep RAS,EX area with Issue Unit and integer, lw/sw, mult and div queues, 32-deep ROB, 48-deep PRF, 16-deep FRL, 8-loc SAB, 4-loc SB and a Copy Free Checkpoint consisting of a Retirement RAT and 8-checkpoint buffers for storing branch ROB, FRL tags for squash on branch mispredictions. Design was coded in VHDL, implemented in Xilinx FPGA and verified using given testbenches and instruction streams.

4) Dual-Core Dual-Threaded In-Order 5-stage Pipeline based Network Processor to implement custom SDN Switch Jan 2014 - May 2014 Designed Verilog RTL for Dual-Core Dual-Threaded 64-bit Network Processor with five stage in-order pipeline with hardware accelerators to realize a custom Controller-based Switch to prevent DOS attack through Honeypot application with additional network security feature through Deep Packet Inspection. Perl translator used to generate machine code from GCC MIPS 32 compiler for the processor’s MIPS32 ISA subset. Design implemented in Xilinx Virtex II based NetFPGA board and tested in live experimental network cluster to prove functionality.

5) Full custom Design and Layout with optimization for a 64-bit Multicycle CPU at 1.6ns Clock (180nm technology) Apr 2014 - May 2014 Designed schematic,DRC check and layout with LVS match of EX and MEM stages in full-custom transistor in 180 nm technology, with Area, Delay and Power Optimization, for a 64-bit multicycle CPU that included: - 4 bank 64-bit wide 1Kbit single-port Read/Write SRAM, Datapath including: 64-bit ALU (with functional units of 64-bit OR, AND, XOR and Kogge-Stone tree adder) and a 16-bit divider. Area and Power optimization ideas like clock gating, SRAM enable signal and data recirculating muxes, and Delay optimization ideas like use of Dynamic CMOS logic, fast tree adder, pipelining of SRAM circuitry. IF, ID stages of the CPU realized through Perl script while EX and MEM stages designed in layout.

ADDITIONAL INFORMATION

Worked as Deputy Manager of ‘Workshops Committee’ in a National Inter-college technical festival, Pragyan 2010. Worked as Coordinator of ‘Public Relations’ in a National Inter-college cultural festival, Festember 2008. Member of CRY – CHILD RIGHTS AND YOU, NIT Chapter, Aug 2008-Apr 2011. Interests include swimming, playing cricket and badminton, reading books and watching movies.