Yiming Cao
**** **** **** **. *** #** Los Angeles, CA90007 acfwsa@r.postjobfree.com Tel: 213-***-****
Career Objective
Seeking a fulltime/intern position in ASIC design/verification
Core Qualification
Solid working experience with RTL design and verification using Verilog, System Verilog, VHDL and UVM.
Proficiency with EDA tools: Design Compiler, ModelSim, Xilinx ISE, NC-Verilog, Cadence Virtuoso, Spectre.
Have solid knowledge in computer architecture, such as Tomasulo processor, pipeline, CMT, MOESI, FIFO.
Familiar with software and hardware language: Verilog, System Verilog, UVM, VHDL, Perl, Python, C++ and Java.
Familiar with RTL design in FPGA and FPGA Prototyping.
Education
M.S Electrical Engineering, GPA: 3.43 Expected Graduation: Dec 2014
University of Southern California
Core Courses:
VLSI System Design (EE577A/EE577B) Digital System Design (EE560) Computer System Architecture (EE557)
Programming Systems Design (CSCI455) Computer System Organization (EE457) MOS VLSI Circuit Design (EE477)
B.S Measurement and Control Technology and Instrument, GPA: 3.65 June 2012
Wuhan University of Technology
Academic Project Experience
06/2014-08/2014
Tomasulo Algorithm for RISC Processor (Nexys4 FPGA board, Xilinx ISE, Modelsim, VHDL)
Implemented an out-of-order execution, in-order-completion pipelined CPU which can support MIPS ISA.
Implemented synthesis and post-synthesis and tested on the Xilinx ISE with Artix7 FPGA board.
Introduction to Verification Using UVM/System Verilog (NC-Verilog Simulator) 02/2014-05/2014
Implemented test bench for FIFO including driver, monitor, sequencer, etc in both UVM and System verilog.
Verified adder by using assertions and generated code coverage test by using coverage group in SystemVerilog
FPGA prototyping Lab (NC-Verilog, Xilinx ISE, Modelsim, Verilog) 04/2014-05/2014
Verified a traffic light design by using FPGA prototyping. Improved code coverage and decreased power of design
Simplified Built-in Self Test Design(NC-Verilog, System Verilog) 03/2014-04/2014
Designed an adder using LFSR(linear feedback shift-register) as the test input
03/2014-04/2014
Introduction to C++ Design(Visual Studio, C++)
Designed a console-based grade management system
02/2014-03/2014
Statistical Analysis and Pattern Recognition(Python)
Analyzed statistical properties and recognized data pattern by using Python.
02/2014-03/2014
Bilinear Interpolation of NLDM using Perl (Perl)
Designed a more elaborated NLDM table, using Perl to bilinear interpolate data into the original NLDM table.
Digital Logic Design Lab (NC-Verilog, Verilog) 01/2014-03/2014
Designed synchronous/asynchronous parameterized FIFO
Implemented bus arbiter, LRU (Least Recent Used) priority encoder, PSP (Parallel -Serial-Parallel) Transmitter
Designed a generl-purpose ternary content-addressable memory (TCAM) including an LRU