| Resume alert | Resumes 11 - 20 of 1654 |
First Class Front End
Hyderabad, Telangana, India
... AutoCAD, Microstation, Bentley Navigator, SpatialNET EDA Tools : Xilinx Vivado/ISE, ModelSim, ALDEC ALINT, LDRA, ADSP, Active HDL FPGA : Xilinx Spartan 3E/ Spartan 6/ Kintex7/ Artix7 Academic Qualifications M.Tech in VLSI System Design from Aurora’s ... - 2023 Sep 19
... AutoCAD, Microstation, Bentley Navigator, SpatialNET EDA Tools : Xilinx Vivado/ISE, ModelSim, ALDEC ALINT, LDRA, ADSP, Active HDL FPGA : Xilinx Spartan 3E/ Spartan 6/ Kintex7/ Artix7 Academic Qualifications M.Tech in VLSI System Design from Aurora’s ... - 2023 Sep 19
Control Systems Fpga Design
Visakhapatnam, Andhra Pradesh, India
... - 7.0 Specializations Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx Vivado Projects (using Verilog and implemented ... - 2023 Sep 11
... - 7.0 Specializations Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx Vivado Projects (using Verilog and implemented ... - 2023 Sep 11
Software Engineer Class X
Anjanadri Layout, Karnataka, 560062, India
... Other Tools: Kafka, Git, GitHub, Bit Bucket, Docker, Kubernetes, AWS, Azure PROJECTS UNDERTAKEN Line following abstract detecting &deviating, boundary detecting BOT Implementation of FPGA to Realize Fingerprint Verification with Optimal Computation. ... - 2023 Sep 04
... Other Tools: Kafka, Git, GitHub, Bit Bucket, Docker, Kubernetes, AWS, Azure PROJECTS UNDERTAKEN Line following abstract detecting &deviating, boundary detecting BOT Implementation of FPGA to Realize Fingerprint Verification with Optimal Computation. ... - 2023 Sep 04
Associate Software Developer
Bangalore, Karnataka, India
... ACADEMIC PROJECTS ● 1 D Time-Domain Convolution Using FPGA Implemented a custom accelerator circuit in VHDL on the Zedboard to obtain convoluted outputs for a given input. Designed and implemented signal buffer, kernel buffer and the convolution ... - 2023 Mar 25
... ACADEMIC PROJECTS ● 1 D Time-Domain Convolution Using FPGA Implemented a custom accelerator circuit in VHDL on the Zedboard to obtain convoluted outputs for a given input. Designed and implemented signal buffer, kernel buffer and the convolution ... - 2023 Mar 25
Test Engineer Data
VasanthaNagar, Karnataka, India
... RTAX2000S FPGA used for command, control,signal processing and interfacing applications and high resolution sensors used in satellite systems. Roles and responsibilities: Satellite Telemetry cards Testing Testing documents preparation Verification ... - 2023 Feb 26
... RTAX2000S FPGA used for command, control,signal processing and interfacing applications and high resolution sensors used in satellite systems. Roles and responsibilities: Satellite Telemetry cards Testing Testing documents preparation Verification ... - 2023 Feb 26
Content Writer Scientific Research
Sector 56, Haryana, India
... using Artificial Intelligence ( M.Tech ) A Report on the FPGA Implementation after designing the Stop Watch Controller Components and its top level Design (B.Tech) a) Design, Estimation and Fabrication of Automatic and Autocut Voltage Stabilizer. ... - 2023 Feb 10
... using Artificial Intelligence ( M.Tech ) A Report on the FPGA Implementation after designing the Stop Watch Controller Components and its top level Design (B.Tech) a) Design, Estimation and Fabrication of Automatic and Autocut Voltage Stabilizer. ... - 2023 Feb 10
Sec School Matric
Coimbatore, Tamil Nadu, India
... 95 2016 TECHNICAL SKILLS C C++ Basics of Python SQL PCB board designing Matlab LabView PROJECT Title : Infrared Thermography of Undercoating Corrosion Domain : Image Processing PAPER PRESENTATION Presented a paper titled “FPGA IMPLEMENTATION OF AN ... - 2022 Nov 13
... 95 2016 TECHNICAL SKILLS C C++ Basics of Python SQL PCB board designing Matlab LabView PROJECT Title : Infrared Thermography of Undercoating Corrosion Domain : Image Processing PAPER PRESENTATION Presented a paper titled “FPGA IMPLEMENTATION OF AN ... - 2022 Nov 13
Salesforce Developer Ashok
Nagpur, Maharashtra, India
... Tools Worked on ● Salesforce.com, Data Loader, VS Code, Workbench, Proteus, Microwind, MATLAB, Tanner, Eagle, Spartan-E, FPGA, Eclipse Organizational Scan ● Company: Larsen and Toubro Defense Talegaon Pune (6 months Feb-July 2019) Project: K9 ... - 2022 Jun 29
... Tools Worked on ● Salesforce.com, Data Loader, VS Code, Workbench, Proteus, Microwind, MATLAB, Tanner, Eagle, Spartan-E, FPGA, Eclipse Organizational Scan ● Company: Larsen and Toubro Defense Talegaon Pune (6 months Feb-July 2019) Project: K9 ... - 2022 Jun 29
Electronics Engineer Design
Vasanth Nagar, Karnataka, India
... Programming knowledge in ATMEL- FPGA/AVR family of FPSLIC processors (AT94K05, AT94K10). Programming in SoC, XILINX FPGA and CPLDs - family (Zync7,7000, Ultra, Ultra Plus, XC2V500-5-FG456, XC95288XL-7-PQ208, XCS20-PQ208) and its related High speed ... - 2022 Jun 08
... Programming knowledge in ATMEL- FPGA/AVR family of FPSLIC processors (AT94K05, AT94K10). Programming in SoC, XILINX FPGA and CPLDs - family (Zync7,7000, Ultra, Ultra Plus, XC2V500-5-FG456, XC95288XL-7-PQ208, XCS20-PQ208) and its related High speed ... - 2022 Jun 08
Ece Telugu,Kannada,English,Hindi
Bangalore Rural, Karnataka, India
... 2.All MS Office read &write(word,excel,powerpoint…etc) 3.Done training of Python,c & c++ 4.Done projects upon embedded system AND FPGA based Certification: 1.PYTHON PROGRAMMING: The training consisted of Introduction to Python, Using Variables in ... - 2022 Apr 02
... 2.All MS Office read &write(word,excel,powerpoint…etc) 3.Done training of Python,c & c++ 4.Done projects upon embedded system AND FPGA based Certification: 1.PYTHON PROGRAMMING: The training consisted of Introduction to Python, Using Variables in ... - 2022 Apr 02