| Resume alert | Resumes 51 - 60 of 1654 |
Embedded System Project Development
Hyderabad, Telangana, India
... • Developed Working Prototypes using, Java, CSS, HTML 5, My SQL,Embedded C, FRDM- KL25Z, ESP8266, Verilog, Xilinx FPGA. • Good exposure on Qualcomm – QXDM, QCAT, ELT, QCAP, QPST, MediaTek- ELT & Wire- shark Tools. • Practical Knowledge on Real Time ... - 2021 Jun 02
... • Developed Working Prototypes using, Java, CSS, HTML 5, My SQL,Embedded C, FRDM- KL25Z, ESP8266, Verilog, Xilinx FPGA. • Good exposure on Qualcomm – QXDM, QCAT, ELT, QCAP, QPST, MediaTek- ELT & Wire- shark Tools. • Practical Knowledge on Real Time ... - 2021 Jun 02
Lead Engineer House Manager
Vasant Nagar, Karnataka, India
... VectorTools - CANape Language Embedded C, C++, Assembly language, Perl scripting, Python, Java Controllers MCS-51, CalmRISC, ARM, FPGA Operating System Smart card proprietary OS (RTOS), Storage OS, QNX Protocols RS232, RS485, I2C, SPI, CAN protocols ... - 2021 May 30
... VectorTools - CANape Language Embedded C, C++, Assembly language, Perl scripting, Python, Java Controllers MCS-51, CalmRISC, ARM, FPGA Operating System Smart card proprietary OS (RTOS), Storage OS, QNX Protocols RS232, RS485, I2C, SPI, CAN protocols ... - 2021 May 30
Content Writer Trainee
New Delhi, Delhi, India
... Mary's Senior Seconday School 83.4% WORK EXPERIENCE IT Title/Position VVDN Technologies/Embedded Software Engineer 01/2021 - Present, Knowledge of 5g technology Solutions using FPGA technology PROFESSIONAL SKILLS Core Java Basics of C SQL Basics of ... - 2021 May 29
... Mary's Senior Seconday School 83.4% WORK EXPERIENCE IT Title/Position VVDN Technologies/Embedded Software Engineer 01/2021 - Present, Knowledge of 5g technology Solutions using FPGA technology PROFESSIONAL SKILLS Core Java Basics of C SQL Basics of ... - 2021 May 29
Sql server
Hyderabad, Telangana, India
... VLSI project on FPGA based high speed IEEE 754 double precision floating point multiplier using Verilog. 2. Safety & Security Vehicle Based Parking System TECHNICAL SKILLS: C & SQL TECHNICAL ACHIEVEMENTS: Participated in “CIRCUIT DESIGN” ... - 2021 May 25
... VLSI project on FPGA based high speed IEEE 754 double precision floating point multiplier using Verilog. 2. Safety & Security Vehicle Based Parking System TECHNICAL SKILLS: C & SQL TECHNICAL ACHIEVEMENTS: Participated in “CIRCUIT DESIGN” ... - 2021 May 25
Controller Project
Hyderabad, Telangana, India
... 84% High School SSC 2011 60% ACADEMIC PROJECTS Design and implementation of random number generator on FPGA This Project is to generate random bits up to256 Application for this project security Advantages of our project is fast data transmission. ... - 2021 May 21
... 84% High School SSC 2011 60% ACADEMIC PROJECTS Design and implementation of random number generator on FPGA This Project is to generate random bits up to256 Application for this project security Advantages of our project is fast data transmission. ... - 2021 May 21
C, Python, Verilog, Quality Assurance, Testing
Pune, Maharashtra, India
... 4) Boards: FPGA (Xilinx Spartan 3E and Zybo Z10), iMX8M (PCIE-UART, SD-SD, SD-UART) 5) BUS Protocols: I2C, SPI EDUCATION: 1) Master of Technology • 2019 - 2021 • NIT Kurukshetra Embedded System Design with current CGPA of 8.88 2) Bachelor of ... - 2021 May 20
... 4) Boards: FPGA (Xilinx Spartan 3E and Zybo Z10), iMX8M (PCIE-UART, SD-SD, SD-UART) 5) BUS Protocols: I2C, SPI EDUCATION: 1) Master of Technology • 2019 - 2021 • NIT Kurukshetra Embedded System Design with current CGPA of 8.88 2) Bachelor of ... - 2021 May 20
Ece Java
Sambra, Karnataka, India
... FPGA Implementation of Adaptive DCT Image Filter Using Prewitt Edge Detection. PERSONAL DETAILS: Name Laxman Balaraddi. Date of Birth 10-05-1997. Father’s Name Vittal. Mother’s Name Indravva. Nationality Indian. Gender Male. Languages Known Kannada, ... - 2021 May 20
... FPGA Implementation of Adaptive DCT Image Filter Using Prewitt Edge Detection. PERSONAL DETAILS: Name Laxman Balaraddi. Date of Birth 10-05-1997. Father’s Name Vittal. Mother’s Name Indravva. Nationality Indian. Gender Male. Languages Known Kannada, ... - 2021 May 20
C,Java,Python
Hyderabad, Telangana, India
... OS : UNIX Project Details Project1: Title: Audio signal processing Tools: Incisive, Genus, Tempus, Innovus, Vivado, Matlab - Simulink Description: As per the requirements, Implemented the design both on FPGA and PD. Designing a controller which acts ... - 2021 May 19
... OS : UNIX Project Details Project1: Title: Audio signal processing Tools: Incisive, Genus, Tempus, Innovus, Vivado, Matlab - Simulink Description: As per the requirements, Implemented the design both on FPGA and PD. Designing a controller which acts ... - 2021 May 19
Public School Vlsi
Faridabad, Haryana, India
... Digital alarm clock, Static Timing Analysis Completed My Summer Internship From 3ST Technologies and learned about VLSI Front end designing techniques, Worked on Timing analysis with FPGA Synthesis of code and also learned basic of shell scripting. ... - 2021 May 14
... Digital alarm clock, Static Timing Analysis Completed My Summer Internship From 3ST Technologies and learned about VLSI Front end designing techniques, Worked on Timing analysis with FPGA Synthesis of code and also learned basic of shell scripting. ... - 2021 May 14
Techincal Engineer
Chennai, Tamil Nadu, India
... Educational Qualifications: Bachelor of Engineering (Electronics & Telecommunication) from University of Mumbai in year 2018 • Academic Projects Summary: Project Name: Elevator Controller Using FPGA As a part of final year project our group has ... - 2021 May 14
... Educational Qualifications: Bachelor of Engineering (Electronics & Telecommunication) from University of Mumbai in year 2018 • Academic Projects Summary: Project Name: Elevator Controller Using FPGA As a part of final year project our group has ... - 2021 May 14