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First Class Front End

Location:
Hyderabad, Telangana, India
Posted:
September 19, 2023

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Resume:

KOTTUR VISHAL KUMAR

Mobile: +91-903******* Email: ********@*****.***

Career Objective To lead a challenging career in an Esteemed Organization which an opportunity provides for me to learn and where I can contribute my technical skills as professional for the growth of the organization.

Experience Summary

4+ years experience in VLSI Front End Design.

RTL Design using VHDL/Verilog.

Synthesis and Simulation using Xilinx ISE, Vivado & Modelsim.

RTL development, resolving system level challenges, architecting, implementing, and documenting using Verilog/VHDL concepts.

The programming of FPGAs (Spartan6, Kintex7, Artix7) with the help of VHDL/Verilog.

Waveform debug skills using front end industry standard design tools like Xilinx ISE/ Vivado/Modelsim. Testbench/Stimulus Creation, Functional Simulation, Debugging and good understanding of design issues in RTL. Documentation generation: Requirements, design specifications.

Hardware/Firmware Design, Independent Verification & Validation as per DO-254 Standard.

Code walk through, Firmware Testing to certify Airborne System using DO-254 Standard.

Software IV&V as per DO-178B Standard.

Environmental Testing as per DO-160G Standard.

2+ years experience in GIS and CAD fields namely in Redrafting, Migration and GIS model projects for major telecommunications and broadband services.

Work Experience

Name of Concern : Processware Systems PVT LTD, Bengaluru Position : RTL Design, IV&&V Engineer Period : June 7, 2021 to till now Client : CEMILAC (DRDO), Bengaluru Work Location : RCMA (CEMILAC, DRDO), C/O HAL, Bala Nagar, Hyderabad Notice period : Immediately available Name of Concern : Trylogic Soft Solutions AP PVT LTD, Hyderabad Position : Associate VLSI Engineer (RTL Design) Period : November 24, 2016 to October 20, 2019 Number of Months : 2 years 11 months

Name of Concern : Apex Knowledge & Technology Private Limited, Hyderabad Position : Jr. CAD/GIS Engineer Period : September 12, 2013 to November 14, 2015 Number of Years : 2 years 3 months Software Skills Languages : VHDL, Verilog Drafting Tools : AutoCAD, Microstation, Bentley Navigator, SpatialNET EDA Tools : Xilinx Vivado/ISE, ModelSim, ALDEC ALINT, LDRA, ADSP, Active HDL FPGA : Xilinx Spartan 3E/ Spartan 6/ Kintex7/ Artix7

Academic Qualifications

M.Tech in VLSI System Design from Aurora’s Engineering College, Bhongir (Affiliated to JNTU, Hyderabad) with First Class with Distinction 74.88% passed out in December, 2012.

B.Tech in Electronics & Communication Engineering from Aurora’s Scientific, Technological and Research Academy, Hyderabad (Affiliated to JNTU, Hyderabad) with First Class 65.03% passed out in 2010.

Intermediate in M.P.C from Deeksha Junior College, Nirmal (BIE) with First Class with Distinction 88% passed out in 2006.

S.S.C from Sri Saraswathi Shishu Mandir, Nirmal (BSE) with First Class with Distinction 87.33% passed out in 2004.

Projects Projects: Processware Systems PVT LTD

M&DP of CIT for Aircraft

Sarakshi _ Samudrika: ESM for Aircraft

Sarang _ Samudrika: ESM for Helicopter

Nikash_ Samudrika: ELINT for Aircraft

Navachakshu: ESM for Aircraft

Projects: TSS AP PVT LTD

Area-Efficient Adder-Based Sign Detector for RNS

Efficient Design for Convolutive Blind Source Separation

Projects: AKT PVT LTD

GIS Model for Comcast Cable TV and Packet Data

GIS Model for Verizon Telecom Network

Academic Projects:

Efficient FPGA based Distributed Arithmetic Architecture for FIR Filter

Distributed Arithmetic Architecture for FIR Filter

Achievements

NCC ‘A’ Certificate, Camp Certificate (at Adilabad, 32 Andhra Battalion), won prize in group singing competition and as a volunteer in State Level Volleyball Tournament.

Participated in the adjunct course on HDL for Chip Design in AEC, Bhongir.

Participated in the workshop on Advanced VLSI System Design using SYNOPSYS Tools in AEC, Bhongir.

Declaration I hereby declare that above-mention information is correct to the best of my knowledge and bear the responsibility for the correctness of the above mentioned particulars.

Date: / / yours faithfully Place: KOTTUR VISHAL KUMAR



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