Associate Software Developer

Abha Singh

Gainesville, Florida *******@***.*** +1-352-***-**** linkedin.com/in/abhasingh-jr

EDUCATION

● University of Florida, Gainesville, FL, USA Aug 2022 – May 2024 Master of Science in Electrical and Computer Engineering CGPA: 3.55/4 Course work: Reconfigurable Computing, Computer Architecture, Very Large-Scale Integrated Circuits (VLSI), Reconfigurable Computing2, System On Chip, Semiconductor Device Fabrication Lab.

● SRM Institute of Science and Technology, Chennai, India July 2014 - June 2018 Bachelor of Technology in Electrical and Electronics Engineering CGPA: 9.1/10 Course work: Digital Systems, Power Electronics, Microcontroller and Microcontroller, Electrical Machines, Probability and Statistics, Discrete Mathematics, Transmission and distribution, Analog and Digital Circuits. SKILLS

Programming Languages: C, C++, Embedded C, HTML, Python, OpenCL EDA Tools: Xilinx Vivido, ModelSim, Quartus Prime, Cadence Virtuoso HDLs: VHDL, System Verilog, Verilog, UVM

Automotive Tools: CATCH, MKS, GitHub, ER-Tools, PARAD Merge, Datalyser Protocols: I2C, SPI, UART, TCP/IP

WORK EXPERIENCE

Technical Specialist Continental AG, Bengaluru, India January 2021 – July 2022 Customer: PSA France, Maserati Italy, Changan Japan, Honda Japan

● Single point of contact for ASPICE activity at TCI, Bengaluru. Handled SWE.3 and SWE.4 ASPICE documentation with > 95 % coverage achieved for Continental Base Projects. Coached, monitored, guided, evaluated new joiners.

● Collaborated on customer requirements with stakeholders from Frankfurt and Yokohoma. Authoring system level requirements

(FRSR2) for customer specific changes. Further refined into software level requirements (SRS3).

● Responsible to handle new customer requirements. Provide support for other team members by reviewing work products and supporting software release activities. Organized SW bootcamp at TCI, Bengaluru Tools: MKS-RM, ISO26262, ASPICE

Associate Software Engineer Continental AG, Bengaluru, India December 2018 – December 2020 Customer: Honda Japan, Mitsubishi Motor Corporation Japan, SAIC Motors China

● Undertook an analysis of customer requirements and prepared a detailed design for the new change that was requested on my part as a software developer.

● Analyzed cross-functional dependencies, organized meetings to discuss the impact of cross-functional dependencies. Several critical issues were resolved at key junctures during the project.

● Developed better test cases for vehicle testers to consider the system level impact of their tests. Prior to vehicle testing, changes made to the software were tested in SIL / Component test / PATS. Assist VT/SIL/HIL in analyzing the requirements before CVT by assisting with their analysis

Graduate Engineering Trainee Continental AG, Bengaluru, India July 2018 – November 2018

● Learned Vehicle dynamics. Attended risk management, people management, emotion management, scrum handling. Demonstrated and coordinated quick learning skills with team members and completed mini project. ACADEMIC PROJECTS

● 1 D Time-Domain Convolution Using FPGA

Implemented a custom accelerator circuit in VHDL on the Zedboard to obtain convoluted outputs for a given input. Designed and implemented signal buffer, kernel buffer and the convolution pipeline and tackled metastability issues during Clock Domain Crossing using FIFO. Optimized the circuit to obtain parallelism with a 14x speed upgrade when compared to the software implementation of the output.

Languages and Tools: VHDL, C++, ModelSim, Xilinx Vivado

● Design and Implementation of 8x4 SRAM block using 45nm technology node Designed a functional 8x4 SRAM 6T cell layout and schematic to write, read and store data using 45 nm manufacturing technology. Successfully tested the functionality of sensing amplifiers, decoders, and the read/write circuit. Optimized the design and performed DRC and LVS checks for the decoders and the SRAM array. Languages and Tools: Cadence Virtuoso

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