APEKSHA PARATE

Email: adrkdg@r.postjobfree.com Phone No. 775-***-****, 983-***-****

Address: **-*, *** ****** *********, Trimurti Nagar Nagpur-440022 Master’s Degree in Microelectronics and VLSI Design with 1.5 year of Experience as Salesforce Developer/ Administrator/Configuration and Force.com platform. Fluent in English and Hindi with excellent communication and interpersonal skills. A fast learner with strong time management and multitasking skills. Strong work ethic in the team or individual settings to drive product success efficiency. Strong troubleshooting and problem-solving skills with an analytical mindset. Professional Snippets

Listenlights Pvt Ltd, Mumbai: Salesforce Developer Duration: 5th April 2021 - Current

Designed and Implemented Custom objects, Page layouts, Custom tabs, Components.

Developed and Customized UI panels using Visualforce, Apex controllers

Designed Workflow rules, Validation rules, Assignment rules, email alerts and templates, Approval Process based on Business needs.

Worked on the designing of custom objects, custom fields, Role-based page layouts, Custom Tabs, custom reports, report folders, report extractions to various formats, design of Visual Force Pages, Dashboards and various other components as per the client and application requirements.

Created Reports and Dashboards to drive key business decisions.

Maintain user roles and profiles, security settings, access settings etc. (User Profiles, Role Hierarchy, Sharing Rules and Security)

Developed salesforce Lightning applications using Lightning Components (LWC), Controllers and Events and used custom CSS in the components

Writing Apex Triggers and Controller classes by keeping in mind SFDC governor limits.

Involved in writing test classes for all apex classes. Achieving Test Converge more than 75% and maintaining the same at the time of enhancements and Preparation of Unit Test Plans.

Writing Batch Classes and Schedule classes.

Development experience in HTML, Java, Apex, Visual Force, JavaScript and SQL/SOQL

Hands-on experience in Mass Data Migrations using different data migration tools. Academic Highlights

● M-Tech Electronics and Communication Engineering (Microelectronics and VLSI Design) 2019 CGPA: 8.32 MIT-ADT School of Engineering, Loni, Kalbour-Pune

● B.E Electronics Engineering 2016 CGPA: 7.49 Rajiv Gandhi College of Engineering and Research, Nagpur

● HSC General Science 2012 CGPA: 6.00 Santaji Mahavidyalaya, Nagpur

● SSC Science 2010 CGPA: 6.00 Kendriya Vidyalaya O.F Ambajhari, Nagpur Technical Competencies

Salesforce Apex, Trigger, SOQL/SOSL and Visualforce

● Lightning Web Components (LWC)

● Salesforce DX

Testing Debugging

JavaScript

Tools Worked on

● Salesforce.com, Data Loader, VS Code, Workbench, Proteus, Microwind, MATLAB, Tanner, Eagle, Spartan-E, FPGA, Eclipse

Organizational Scan

● Company: Larsen and Toubro Defense Talegaon Pune (6 months Feb-July 2019) Project: K9 Vajra-T

Role and Responsibilities: Designed the debug flow chart for more than 10 modules of K9 Vajra-T and successfully completed the testing of all the modules.

● Company: Larsen and Toubro Defense Talegaon Pune (1 month June-July 2018) Project: Pinaka

Role and Responsibilities: Manufacturing, Designing, and Testing of Modules Academic Projects

● Title: To design 12-bit low power and low voltage segmented successive approximation registers analog-to-digital converter on 45nm CMOS technology.

Year: 2019

Description: The design uses an efficient SAR to reduce power consumption due to the capacitive array compared to conventional design as well as reducing the total capacitor area by half. The ADC utilizes a segmented capacitive DAC array, Dual tail comparator, and SAR circuit containing D-flip-flops. In research, the dynamic comparator expends lower control when contrasted with different methodologies. Along with these, different models of the dual tail comparator are proposed and compared with respect to the power used, speed, and accuracy. This research introduces the execution of 12-bit SAR-ADC working at 50MHz frequency and supply voltage 0.3V in 45nm CMOS Technology. Various designs of double rail-tail comparators were executed and compared with power, rail, accuracy, and die size. Therefore, the dynamic double tail comparator was chosen to design the ADC.

● Title: To design the prototype of the Lift Controller on an FPGA. Year: 2018

Description: To design the 3-floor lift controller using VHDL code and simulate it on FPGA Board (Spartan 3E).

● Title: Driver Assistance System.

Year: 2015

Description: A driver assistance system is used for helping drivers while driving and to prevent accidents. There are several safety modules included like the Alcohol test, Seat Belt warning system, obstacles detector, Reverse parking along with the Lane-keeping system.

● Title: Automatic Street Light Control System.

Year: 2014

Description: Automatic-street light control system uses a transistor as a switch to ON and OFF the street light automatically. The system itself detects whether there is a need for light or not. When darkness rises then automatically street light is switched ON, and when another source of light it gets OFF. Research Work/Paper Published

● Apeksha Parate, Ashish Panat, Reena Gunjan, “To design 12-Bit Low Power and Low Voltage Segmented Successive Approximation Register Analog-to-Digital Converter on 45nm CMOS Technology”, IJREAM ISSN:2454-9159, Volume 05, Issue 08, Nov 2019. DOI:10.35291/2454-9150.019.0499

● Apeksha Parate, Ashish Panat, Reena Gunjan, “A Review on 12-Bit Low Power and Low Voltage ADC with Noise Optimization.” Universal Review-Journal, Volume VIII, Issue 11, February 2019. DOI:16.10089/URJ Achievements

● Received Award for Planning week in Listenlights Pvt Ltd.

● Received Award for the highest rank in the department.

● First prize in Calligraphy and Group Song.

Extracurricular Activities

● Senior Organizer of “Mini and Major Project” event held in Persona-2018 at SOE, MIT-ADT Pune.

● Participated in a workshop on “Embedded Product Design” organized by the Electronics Department.

● The organizer of the “Box Cricket League” event held in SPARK-15 at Rajiv Gandhi College Of Engineering And Research, Nagpur

● The organizer of Dance in “Malhar-15”.

● The organizer of the “Quizzaire” event held in SPARK-14 at Rajiv Gandhi College of Engineering And Research, Nagpur.

Core Competencies

Hard Worker, Decision maker

Collaborative, Leadership Quality

Multi-tasking, Time management

Attentive, Effective communication skills

Ability to learn and adapt to new technologies quickly

Ability to work under pressure

Areas of Interest

● Photography

● Singing

● Crafting

● Dancing

Personal Profile

● Father’s Name: Mr. Ashok R. Parate

● Mother’s Name: Mrs. Kanta A. Parate

● Date of Birth: 06-06-1994

Declaration:

I hereby affirm that the Information furnished above is correct and complete to the best of my knowledge. Place: Nagpur (Apeksha A. Parate)

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