Control Systems Fpga Design

Personal Details

Date of birth:

October **,****

Mobile:

+91-765*******

Email:

********@*****.**

Address:

**-***,***************,*******,

Visakhapatnam,530040,andhrapradesh

Languages Spoken

English

Telugu

Hindi

Activities

Boxing

Bike Riding

CHEALLURI UMA MAHESH

Professional Goals

Desire to implement and strengthen the cognition acquired in VLSI, utilize these skills as an engineer in your esteemed organization for correlative growth.

Internship

Title: A STUDY OF FIELD INSTRUMENTS & DISTRIBUTED

CONTROL SYSTEMS ASSOCIATED WITH ONLINE CRUDE

BLENDING.

Client: HINDUSTAN PETROLIUM CORPORATION LIMITED

Academic Details

GITAM Institute of Technology

(Present)

MTECH VLSI Design 2022 – 2024

CGPA – 8.44

GITAM Institute of Technology

BTECH ECE 2016 - 2020

CGPA – 6.49

NRI Junior College

Board of Intermediate Education, AP - MPC 2014 – 2016 Percentage – 74.60%

VISWA VIGNAN VIDYALAYAM School

Board of Secondary Education, AP 10th grade (2014) CGPA - 7.0

Specializations Areas of interest

Technical Skills: Digital Circuits,Verilog

Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software:

Cadence Virtuoso, TopSpice,

Xilinx Vivado

Projects (using Verilog and implemented in FPGA)

4-bit full adder using 1-bit full adder

Carry Look-Ahead Adder

BCD to 7 segment decoder, 2x4 decoder

8x1 multiplexer using 4x1 and 2x1 multiplexer

D – Latch and flip-flop

Finite state machines (three 1’s detector)

propagation delay and rise time(from transient analysis of first order rc circuit).

Contact this candidate