| Resume alert | Resumes 21 - 30 of 198 |
Engineer Software
Lakewood, CA
... Courses: Embedded Systems, Computer Arch, Data Structures, Algorithms, Logic Design, FPGA, Motors, Power Electronics. Software Projects • Facebook DevPost hackathon: Design and submit software in Python to create a multi-layered convolutional neural ... - 2020 Nov 16
... Courses: Embedded Systems, Computer Arch, Data Structures, Algorithms, Logic Design, FPGA, Motors, Power Electronics. Software Projects • Facebook DevPost hackathon: Design and submit software in Python to create a multi-layered convolutional neural ... - 2020 Nov 16
Student at University of Southern California
Los Angeles, CA
... Artix -7 FPGA Nexys4 Board, Innovus(Automated Place and Route), NCSIM,Design Compiler, Others: GPGPU: SIMT- Stack, Score Board, Task Manager, I-Buffer, Operand Collector Protocols: PCIe, PCI, AXI, MOESI, ACK/NAK, DDR Memory technologies: DDR (I, II, ... - 2020 Oct 22
... Artix -7 FPGA Nexys4 Board, Innovus(Automated Place and Route), NCSIM,Design Compiler, Others: GPGPU: SIMT- Stack, Score Board, Task Manager, I-Buffer, Operand Collector Protocols: PCIe, PCI, AXI, MOESI, ACK/NAK, DDR Memory technologies: DDR (I, II, ... - 2020 Oct 22
Python Manager
Fullerton, CA
... internal ERP system • Worked with SRM provider Jaggaer to enable internal and external suppliers onto UCSD P2P platform PROJECTS FPGA-GPU Research Paper 2/2020 – Current • Working on a research paper with the Pattern Recognition Lab comparing the ... - 2020 Oct 10
... internal ERP system • Worked with SRM provider Jaggaer to enable internal and external suppliers onto UCSD P2P platform PROJECTS FPGA-GPU Research Paper 2/2020 – Current • Working on a research paper with the Pattern Recognition Lab comparing the ... - 2020 Oct 10
Software Developer
Santa Ana, CA
... Architecture, Streaming Multi-Processor Warp Scheduling, Single Program Multiple Data Kernels (SPMD paradigm), GPU vs CPU + FPGA Acceleration, Xilinx/Vitis Workflow, MPI Groups and Communicators, MPI Collective Communication Operations IAN FOSTER’S ... - 2020 Oct 02
... Architecture, Streaming Multi-Processor Warp Scheduling, Single Program Multiple Data Kernels (SPMD paradigm), GPU vs CPU + FPGA Acceleration, Xilinx/Vitis Workflow, MPI Groups and Communicators, MPI Collective Communication Operations IAN FOSTER’S ... - 2020 Oct 02
Electrical Engineer Design
Fullerton, CA
... SKILLS • Signal Processing MATLAB • PCB Circuit Design Altium Designer, Kicad • Microsoft Office • Electronic Circuit Analysis PSPICE, Proteus • Robot Operating System (ROS) • Microcontroller AVR, ARM • FPGA Verilog • AutoCAD • SolidWorks • Fusion • ... - 2020 Sep 15
... SKILLS • Signal Processing MATLAB • PCB Circuit Design Altium Designer, Kicad • Microsoft Office • Electronic Circuit Analysis PSPICE, Proteus • Robot Operating System (ROS) • Microcontroller AVR, ARM • FPGA Verilog • AutoCAD • SolidWorks • Fusion • ... - 2020 Sep 15
Engineer Design
Santa Ana, CA
... Skills Designed: LSI Logic ASIC, Xilinx FPGA, A/D, D/A, CCD, Power Supplies, Fiber Optic, MC68040, PIC, and RISC. Communication: I2C, RS-232, RS-485,RS-422, RS-170, RS-343, and MIL-STD-1553. Standards: AC 43.13, EN4165, ARINC, PXI, EMI, IPC, ANSI, ... - 2020 Aug 10
... Skills Designed: LSI Logic ASIC, Xilinx FPGA, A/D, D/A, CCD, Power Supplies, Fiber Optic, MC68040, PIC, and RISC. Communication: I2C, RS-232, RS-485,RS-422, RS-170, RS-343, and MIL-STD-1553. Standards: AC 43.13, EN4165, ARINC, PXI, EMI, IPC, ANSI, ... - 2020 Aug 10
Electrical Engineer Design
Los Angeles, CA
... Education: Illinois Institute of Technology, Chicago, IL Aug 2016 - May 2018 • Master of Science Electrical Engineering (M.S.E.E.) Major GPA 3.8 Majored in VLSI and Microelectronics with a focus on CMOS circuit design, FPGA, SoC and RTL development ... - 2020 Aug 10
... Education: Illinois Institute of Technology, Chicago, IL Aug 2016 - May 2018 • Master of Science Electrical Engineering (M.S.E.E.) Major GPA 3.8 Majored in VLSI and Microelectronics with a focus on CMOS circuit design, FPGA, SoC and RTL development ... - 2020 Aug 10
Fourth-Year studying B.S. Computer Engineering
Diamond Bar, CA, 91765
... Developed and programmed circuits with PIC18F and C or PIC18F assembly Collaborated with other students FPGA Arithmetic Microcontroller Laboratory Student Jan 2019 - May 2019 Implemented circuit design using Verilog and FPGA Programmed, simulated, ... - 2020 Jul 16
... Developed and programmed circuits with PIC18F and C or PIC18F assembly Collaborated with other students FPGA Arithmetic Microcontroller Laboratory Student Jan 2019 - May 2019 Implemented circuit design using Verilog and FPGA Programmed, simulated, ... - 2020 Jul 16
Design Engineer Engineering
Los Angeles, CA
... Education: Master of Science in Electrical and Computer Engineering, Dec 2019 California State University, Northridge (GPA 3.3/4) Courses: FPGA, System on Chip (SOC), Computer Architecture, Advanced Switching Theory, Digital System Auto VHDL, ... - 2020 Jul 13
... Education: Master of Science in Electrical and Computer Engineering, Dec 2019 California State University, Northridge (GPA 3.3/4) Courses: FPGA, System on Chip (SOC), Computer Architecture, Advanced Switching Theory, Digital System Auto VHDL, ... - 2020 Jul 13
Engineering Computer
Buena Park, CA
... (VHDL), EGCP 441: Advanced Electronics for Computer Engineers, EGCP 446: Advanced Digital Design Using Verilog HDL (FPGA Programming), EGCP 447: Introduction to Hardware Security, EGCP 450: Embedded Processor Interfacing, EGCP 461: Low Power ... - 2020 May 30
... (VHDL), EGCP 441: Advanced Electronics for Computer Engineers, EGCP 446: Advanced Digital Design Using Verilog HDL (FPGA Programming), EGCP 447: Introduction to Hardware Security, EGCP 450: Embedded Processor Interfacing, EGCP 461: Low Power ... - 2020 May 30