| Resume alert | Resumes 41 - 50 of 382 |
Engineering Assistant Drafter
Morgan Hill, CA
... •Included design and building of FPGA, BGA tools for 3D POP IC chip developing R/D group/s •Main duties included design, drafting and detail drawings, responsible for quoting and built fabrication from vendors. •Other duties include facility layout, ... - 2021 Jun 05
... •Included design and building of FPGA, BGA tools for 3D POP IC chip developing R/D group/s •Main duties included design, drafting and detail drawings, responsible for quoting and built fabrication from vendors. •Other duties include facility layout, ... - 2021 Jun 05
Digital and Physical Design Engineer, Verification Engineer
Santa Clara, CA
... HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis) Verification Methodologies: UVM (basics), FPGA Prototyping, Formal Verification, Assertion based Verification Other: ABC Synthesis Tool, AutoCAD, SAL, SPIN, MS Office, ... - 2021 May 30
... HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis) Verification Methodologies: UVM (basics), FPGA Prototyping, Formal Verification, Assertion based Verification Other: ABC Synthesis Tool, AutoCAD, SAL, SPIN, MS Office, ... - 2021 May 30
iOS Developer
San Jose, CA
... Complete, verify and deliver FPGA on schedule. FPGA successfully works with the client's MEMs display. Define the micro-architecture, implement the behavioral models, verify functional blocks, debug and verify thoroughly the design against defined ... - 2021 Mar 03
... Complete, verify and deliver FPGA on schedule. FPGA successfully works with the client's MEMs display. Define the micro-architecture, implement the behavioral models, verify functional blocks, debug and verify thoroughly the design against defined ... - 2021 Mar 03
Engineering Engineer
San Jose, CA
... at University of Massachusetts, 2017-2021 Lecturer at University of Massachusetts for Probability and Statistics, 2019 FPGA Architecture Intern at University of Massachusetts, 2016-2017 Test and Veri cation Intern at University of Massachusetts, ... - 2021 Jan 06
... at University of Massachusetts, 2017-2021 Lecturer at University of Massachusetts for Probability and Statistics, 2019 FPGA Architecture Intern at University of Massachusetts, 2016-2017 Test and Veri cation Intern at University of Massachusetts, ... - 2021 Jan 06
Application Engineer II
Sunnyvale, CA
... Pipelining, Cache •Knowledge on ASIC Design flow - RTL, Synthesis, Simulation, Custom Layout, Logic Equivalence Checking (LEC), Floor Planning, Placement and Routing, Design Compiler Synthesis flow, FPGA Design flow, FPGA Prototyping. SKILLS •EDA ... - 2020 Dec 21
... Pipelining, Cache •Knowledge on ASIC Design flow - RTL, Synthesis, Simulation, Custom Layout, Logic Equivalence Checking (LEC), Floor Planning, Placement and Routing, Design Compiler Synthesis flow, FPGA Design flow, FPGA Prototyping. SKILLS •EDA ... - 2020 Dec 21
Director of Program Management
San Jose, CA
... Hiring and management of a team of 10+ engineers, including ATE, hardware, FPGA, mechanical and PCB design Led the product development process from architecture and specifications through customer shipment within 1 year As Interim Director System ... - 2020 Dec 20
... Hiring and management of a team of 10+ engineers, including ATE, hardware, FPGA, mechanical and PCB design Led the product development process from architecture and specifications through customer shipment within 1 year As Interim Director System ... - 2020 Dec 20
Design Engineering
San Jose, CA
... • Assisted and mentored students in Lab assignments based on Vivado HLS and Basys 3 FPGA. In-plant Trainee, Bharat Electronics Limited, India Nov 2016 - Dec 2016 • Gained knowledge on Development and Engineering department that monitors the tank ... - 2020 Dec 10
... • Assisted and mentored students in Lab assignments based on Vivado HLS and Basys 3 FPGA. In-plant Trainee, Bharat Electronics Limited, India Nov 2016 - Dec 2016 • Gained knowledge on Development and Engineering department that monitors the tank ... - 2020 Dec 10
Python Data
Santa Clara, CA, 95054
... to control the speed and position of servo actuator in the launch vehicle, which is based on a BLDC motor and the whole system was implemented in FPGA EDUCATION M.S., Electrical Engineering (3.75/4.00) San Jose State University, USA Dec 2020 B. ... - 2020 Nov 18
... to control the speed and position of servo actuator in the launch vehicle, which is based on a BLDC motor and the whole system was implemented in FPGA EDUCATION M.S., Electrical Engineering (3.75/4.00) San Jose State University, USA Dec 2020 B. ... - 2020 Nov 18
Sr. Electrical Engineer Design
Campbell, CA
... Extensive expertise across the span of ASIC, FPGA, board and system level design disciplines. Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products. Debugging and test of 100Gbps Ethernet CISCO products. Design and ... - 2020 Oct 23
... Extensive expertise across the span of ASIC, FPGA, board and system level design disciplines. Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products. Debugging and test of 100Gbps Ethernet CISCO products. Design and ... - 2020 Oct 23
Design Engineer Engineering
Los Gatos, CA
... •Built FPGA validation environment with single FPGA board, responsibility includes bit file compilation, programming FPGA, and board level debug for functionality accuracy. •Constructed FPGA & bring up test plans. Executed FPGA validation on new and ... - 2020 Oct 06
... •Built FPGA validation environment with single FPGA board, responsibility includes bit file compilation, programming FPGA, and board level debug for functionality accuracy. •Constructed FPGA & bring up test plans. Executed FPGA validation on new and ... - 2020 Oct 06