SHRIYA PARAG SHAH

** ********** **, ***** *****, CA 95050 admttt@r.postjobfree.com 562-***-**** www.linkedin.com/in/shriya-shahsp Work Authorization : Lawful Permanent Resident of the United States EDUCATION

UNIVERSITY OF SOUTHERN CALIFORNIA Aug 2019 – Dec 2020 Master of Science, Electrical Engineering GPA: 3.63/4 Coursework: Computer Systems Organization EE457, MOS VLSI Circuit Design EE477,Computer Systems Architecture EE557, VLSI System Design (EE577A & EE577B), System Verification EE580, Diagnosis and Design of Reliable Digital System EE658 (DFT related course)

THAKUR COLLEGE OF ENGINEERING & TECHNOLOGY Aug 2015 - May 2019 Bachelor of Engineering, Electronics and Telecommunication Engineering GPA: 9.12/10 TECHNICAL SKILLS

Programming Languages: Verilog, SystemVerilog, Python

Tools: Cadence Virtuoso, QuestaSim, Quartus, HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis)

Verification Methodologies: UVM (basics), FPGA Prototyping, Formal Verification, Assertion based Verification

Other: ABC Synthesis Tool, AutoCAD, SAL, SPIN, MS Office, LaTex WORK EXPERIENCE

VISHAY SEMICONDUCTORS VLSI INTERN Feb 2018 - Dec 2018

Worked on stages of product design and development and created a test plan for electrical designs. Implemented PCB layout designs considering factors of ESD Protection, guard bands and guard rings.

Performed product testing on various types of power capacitors and resistors using Multimeter and CRO. Designed a testbench for testing breakdown capacities of power diodes by generating controlled high voltage and current for testing discrete devices.

Learned about the assembly, device physics and testing summary of various products such as Hockey-Puck, DO’s (diodes), SCR’s, and Studs including their fabrication methods. AIR INDIA LTD ENGINEERING INTERN Dec 2017 - Jan 2018

Assisted the team which was working to develop the software for Air India express.

Worked in electronics lab for Circuit troubleshooting which involved quality and defect rectification of BOEING 400, BOEING 747, BOEING 737 using Signal Generators and Network Analyzer and also repairing of composite material and lubrication of aircraft.

Learnt Traffic Collision Avoidance System (TCAS), Instrument Landing System (ILS) and applied them to test. ACADEMIC PROJECTS

FaultSim: Levelisation, Logic and Fault simulator and ATPG

Worked in a team to develop two ATPG algorithms (D algorithm and PODEM) and two fault simulators.

Learned in-depth about SCOPE measures and tried to implement levelisation in the project. Used ABC Tool to perform translations between various circuit netlist formats (verilog, bench, blif, aig, vhd) of combinational circuits and coded a Bench Translator to convert

.bench circuit netlist file to ckt-658 format .ckt circuit file.

Implemented a python code which generates a testbench for flat gate-level Verilog files of combinational circuits, randomly generates 10000 PI test patterns and obtains golden output results by invoking QuestaSim.

Circuits Used : Benchmarks (ISCAS ’85, EPFL, LG-Synth ’91 which also included large circuits with 16-23 million AND gates). FIFO Design and Verification (UVM SystemVerilog QuestaSim)

Designed a synchronous FIFO and also implemented testbench to verify its functionality using UVM.

Testbench was efficiently written to consider various corner cases like FIFO becoming full to empty or empty to full. Also when FIFO is full and still writing or empty or still reading.

Applied appropriate assertions and covergroups to ensure complete functional coverage and code coverage. FPGA Prototyping of Traffic Light Controller (Verilog Quartus II Altera DE2-115 FPGA Board)

Designed a Finite State Machine Design for Traffic Light Controller along with a testbench in Verilog to verify its functionality.

Synthesized the design for DE2-115 Altera FPGA using Quartus II and achieved a minimum 5.9ns clock period. 5-Stage Pipelined CPU Design (45nm technology Cadence Virtuoso Python )

Designed schematic and layout of a 5-stage pipelined processor in 45nm CMOS technology. Used Front-end Python scripting for IF and ID stage, and Back-end script for generating a vector file and corresponding results for verifying the functionality.

The design was optimized so as to improve the Area x Power x Delay product, this was achieved by using optimization techniques such as clock gating, dynamic logic and time borrowing. TECHNICAL PUBLICATIONS

“Moving Object Detection with Shadow Compression Using Foreground Segmentation” – (IRJET) e-ISSN: 2395-0056 CO- CURRICULAR ACTIVITIES

IEEE-TCET Treasurer from 2016-2018.

Editor of EXTC Department Magazine ‘ABHIVARG’ and also worked as a Climate Counsellor (CC) for ICCE in 2018. CERTIFICATION COURSE

Essential SystemVerilog for UVM v1.2.5rev3 (Cadence Training)

Allegro Design Entry HDL Front-to-Back Flow (Cadence Training)