HARIKA RENDUCHINTALA

+1-408-***-**** adivc7@r.postjobfree.com http://www.linkedin.com/in/harikarenduchintala

PROFESSIONAL SUMMARY

•2+ years of experience coding in Verilog and ASIC/CMOS Design.

•Experience building Universal Verification Methodology (UVM) Testbenches to determine if the DUT works as expected, Functional Verification, SV Assertions, Code coverage.

•Worked on Neural Networks for digit recognition and optimization using pruning and bit-accurate techniques.

•Extensive knowledge of Static Timing Analysis (STA), EDA tools, Computer Architecture; Pipelining, Cache

•Knowledge on ASIC Design flow - RTL, Synthesis, Simulation, Custom Layout, Logic Equivalence Checking (LEC), Floor Planning, Placement and Routing, Design Compiler Synthesis flow, FPGA Design flow, FPGA Prototyping.

SKILLS

•EDA/CAD/Tools : Synopsys VCS, Altera Quartus II 13.0, Design Compiler, HAPS ProtoCompiler, Synplify, Identify, Certify, MATLAB, Xilinx Vivado,

•Languages : Verilog, VHDL, System Verilog, C

•Operating Systems : Linux, Unix, Windows

•Scripting Languages : Python, Perl, Tcl

•Bus Protocols : SPI, I2C, PCI, PCIe, APB, AHB, PC/AT

EDUCATION

San Jose State University, San Jose, CA May 2018

Master of Science, Electrical Engineering GPA: 3.5/4.0

Coursework: Computer Architecture, Emphasis on Digital VLSI design, ASIC CMOS Design, HDL Based Digital Design with Programmable Logic, Analog Circuit Design, Analog Integrated Circuit Layout, Semiconductor Device Theory, SoC Design, Verification with System Verilog, UVM

Jawaharlal Nehru Technological University, Kakinada, India May 2015

Bachelor of Technology, Electronics and Communication Engineering GPA: 3.5/4.0

PROFESSIONAL EXPERIENCE

Application Engineer II, Synopsys Inc, Mountain View, CA November 2018 – Present

Providing technical support to customers for Synopsys FPGA tools like Protocompiler and Synplify. Conducting root cause analysis and providing resolution to customers’ technical issues

Debugging and validating design for FPGA based Synthesis, STA and P&R. Running customer RTL testcases to verify problems, creating work-around when possible; providing feedback to the R&D team on any bugs or enhancements in the tools

Project on UC2 flow with debug using $dumpvars and SVA (System Verilog Assertions)

Project on VC Formal where techniques are used to ensure right functionality of the RTL designs using properties like AEP, coverage analysis, SVA, SEQ, FPV, DPV etc.

Worked on Synthesizing & Partitioning large SOC designs to multiple FPGAs and debugging and validating the design on Hardware

Application Engineer Intern, Synopsys Inc, Mountain View, CA July 2018 – November 2018

•As a part of Verification Group, worked on a project to enable a methodology to prototype using HAPS ProtoCompiler for achieving high performance

•Worked on DC netlist validation flow for HAPS. The goal of the project is to take a DC netlist to ProtoCompiler flow and validate it on HAPS

ACADEMIC PROJECTS

A speed optimization scheme for Convolutional Neural Networks [Quartus II, MATLAB, Verilog]

•Focused on designing Neural Network base model to recognize hand-written digits from 0 to 9

•The algorithm was designed for utilizing minimum hardware for fully connected layers. Used Bit-accurate and Pruning optimization techniques. Analysis was made for the memory cost and observed a decrease without much compromise in accuracy

•Static Timing Analysis was performed for removing any Setup and hold time violations

Implementation of 32-bit Nios 2 RISC processor [Synopsys VCS, Altera Quartus II, Verilog]

•Implemented a subset of Altera Nios 2 Instruction Set architecture and designed as a 5-stage pipelined architecture

•Pipelined design consisted of logic, cycle stalling and forward chaining

•Analyzed that forward chaining mechanism runs at faster clock rate than stalling mechanism though it consumes more area

Design of simple CNN Inference Engine for Character Recognition [Intel Altera Quartus Prime, MATLAB, Verilog]

•Implemented different stages of a Convolutional Neural Network using FIR filter at the input layer with 400 inputs

•Trained coefficient matrices which consists of weights (Theta1, Theta2) were taken after running a MATLAB model and the bit width of coefficients were varied from 4 bits up to 16 bits and Sigmoidal Functions were used at the First and last stages

•Compared the performance in terms of speed, memory and accuracy

Verification of ADC and DAC [Synopsys VCS, UVM, System Verilog]

•Designed a UVM environment which includes sequencer, drivers, monitors and scoreboards connected to an APB Bus Functional Model (BFM) to verify the functionality of ADC and DAC

•Verified the APB BFM for 100% functional coverage and check for protocol violations using assertions

Design of a 32-point Inverse Fast Fourier Transform (IFFT) [Synopsys VCS, Verilog]

•Implemented a 32-bit Inverse Fast Fourier Transform in Verilog HDL, using state machines for collecting the inputs, giving to the butterfly module, collecting the outputs and storing in memory and finally giving the outputs to the output port using pushout signal

•The design was synthesized with 4ns clock period, passing the RTL level and gate level simulations without timing violations

Design of a 64-bit Signed Multiplier and Divider Circuit [Synopsys VCS, Verilog]

•Implemented a 64-bit Signed multiplier and divider circuit and desired Addition/Subtraction Algorithm can be performed using ALU and the entire circuit was modeled at Register Transfer Level (RTL). Performed Pre-Synthesis and Post-Synthesis

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