Ravi Shekhar

Mob No- 734-***-****

Email ID: addx5d@r.postjobfree.com

OBJECTIVE:

To accomplish professional excellence in an organization that proffers capacious opportunity to learn, grow, excel, be instrumental in the success of organization’s aspirations and effectively contribute to the world of technology.

EDUCATION:

Masters in VLSI Design, Manipal University, Manipal Aug 2015

B.E in Electronics & Communication Engineering, VTU, Belgaum Jan 2012

SKILLS:

Good knowledge on ASIC flow, Digital design concepts, Standard EDA tools.

Good understanding in RTL design and verification using Verilog/SV.

Hands on experience in developing verification components using System Verilog and UVM.

Hands on experience in Functional Coverage and assertions.

Knowledge on protocols like AHB, AXI, BLE,PCIe.

Good Programming Skills based on OOP approach.

SoC/IP level understanding of Testbench and Verification environment

TECHNICAL SKILLS:

Software

C

Hardware

Verilog, System Verilog, UVM

Scripting Language

Perl, Shell Scripting

Operating System

Windows, Linux

Tools

Cadence NC Sim, Synopsys VCS, Model Sim, Quartus, Rivera Pro

WORK EXPERIENCE: - 4+ Years

Pozibility Tech Pvt Ltd (Jan 2020 to Present)

Project :

Full Chip verification of Programmable NAND Flash Controller for Microchip Client.(Jan 2020 to May 2020)

In depth Understanding of the architecture flow of the project.

Ran the top level and block level test cases for Buffer manager and list engine blocks.

Developed the testcases at full chip level in C for Buffer manager and link Engine functional unit.

Ran the sample test case for PCIe and debugging for malformed error.

Ran the Regression of PCIe and debugging the errors.

Understanding the PCIe layers and creation of top level test cases.

Performed inbound and outbound message transfer of PCIe and check for errors if present.

Debugging the different functional unit assigned to me.

Smart Soc Solutions (March 2018 to Dec 2019 )

Project :

Verification of Resource Control Hardware (RCH) for Tenuto chip for Qualcomm Client (Oct 2018 to Nov 2019)

Verification of Resource Control Hardware (RCH) in Tenuto chip Project.

Formal verification of RCH sub-blocks (Power domain requester, Power domain controller, CBGC and Power FSM blocks.

Developed UVM Agents for Clock Branch Gating Cells (CBGC) and Power domain requester.

Developed UVM REG MODEL for RCH.

Developed testcases for the Power Domain Controller and CBGC blocks.

Ensured code coverage and Functional coverage were covered properly as per test plan.

Mindtree Limited (Nov 2015 to March 2018)

Project :

Verification of BLUETOOTH 5.0 Extended properties using UVM environment for Renesas Client (Aug 2016 to March 2018)

Good Understanding of BLUETOOTH 5.0 IP.

In depth Understanding of the BLE IP and its Link layer application.

Build Test Bench Env in UVM for BLUETOOTH 5.0 – Physical Layer & Extended properties.

Developed testcases for advertiser and scanner devices using BLE 5.0 protocol.

Created assertions to check interrupt handling and thus ensuring protocol adherence.

Validated the RTL netlist on Altera Quartus 2 boards (FPGA Boards) to check the correct functionality.

Developed testcases for advertiser and scanner devices using BLE 5.0 protocol.

Ensured that Code coverage and Functional Coverage of the BLE 5.0 modules are fully covered.

Built the two sets of sequences in UVM for Advertiser and Scanner in BLE 5.0 IP.

Interact with the Renesas clients for various other issues and fixing it within deadlines.

Received Client appreciation for my work in Bluetooth.

Project :

Verification of AXI 4 Bus protocol (Mar 2016 to July 2016)

Very Good Understanding of the AXI.

Built the Testplan for the Verification of AXI 4 where AXI 4 RTL acted as Slave and TB Environment as a Master.

Developed the TestBench environment for AXI 4 in System Verilog.

Developed test cases to check the features of AXI.

Built the Functional coverage model for AXI to check the features related to Test Plan.

Successful Debugging, if any feature was violated.

Project :

Low power Verification of I2C using UPF 1.0. (Nov 2015 to Feb 2016)

In depth Understanding of the IP’s (APB & I2C).

Design of I2C RTL and Testbench Environment in Verilog.

Developed the low power file for I2C using UPF 1.0.

TRAINING:

Training Program

Date

Cadence System Verilog Training

May 2016

Cadence UVM Training

June 2016

Ravi Shekhar

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