| Resume alert | Resumes 61 - 70 of 234 |
Reliability Test Engineer
Sunnyvale, CA
... P rocess Engineering Intern (June 2016-September 2016, 12 week summer internship) o Developed an optical flip chip process and applying solder wetting in order to achieve self-aligning optical components o Implemented die bonding by surface mount ... - 2018 Feb 01
... P rocess Engineering Intern (June 2016-September 2016, 12 week summer internship) o Developed an optical flip chip process and applying solder wetting in order to achieve self-aligning optical components o Implemented die bonding by surface mount ... - 2018 Feb 01
Chemical Engineering Process
Santa Clara, CA
... Studied about different semiconductor packaging like die over coating, molding & sealing, testing etc. Introduction to Nano Engineering: Good understanding on scanning probe techniques, electron microscopy, atomic force microscopy & miniaturization; ... - 2018 Jan 30
... Studied about different semiconductor packaging like die over coating, molding & sealing, testing etc. Introduction to Nano Engineering: Good understanding on scanning probe techniques, electron microscopy, atomic force microscopy & miniaturization; ... - 2018 Jan 30
Operator Machine
Santa Clara, CA
... EXPERIENCE: ASSEMBLY, 6/2017-PRESENT, FINISAR CORP Final assembly including, die attach, wirebond, cap seal, leak check. FAB OPERATOR, 10/2016-6/2017, WESTERN DIGITAL Fab operator METAL/TFILM area, certified BALZERS CORONA sputter. FAB OPERATOR, 11 ... - 2018 Jan 09
... EXPERIENCE: ASSEMBLY, 6/2017-PRESENT, FINISAR CORP Final assembly including, die attach, wirebond, cap seal, leak check. FAB OPERATOR, 10/2016-6/2017, WESTERN DIGITAL Fab operator METAL/TFILM area, certified BALZERS CORONA sputter. FAB OPERATOR, 11 ... - 2018 Jan 09
Data Security
Los Altos, CA
... ● Machine learning models of Apple memory, BICS3 reliability, die sort parameters tuning(LASSO, XGBoost, Ranger) ● ML performance a deep analysis of the HTPD/RTPD/LTPD test data to define a model of FBC growth rate across the temperature. ● Memory ... - 2017 Dec 29
... ● Machine learning models of Apple memory, BICS3 reliability, die sort parameters tuning(LASSO, XGBoost, Ranger) ● ML performance a deep analysis of the HTPD/RTPD/LTPD test data to define a model of FBC growth rate across the temperature. ● Memory ... - 2017 Dec 29
Engineer Manager
San Jose, CA
... 8 Equipment Engineers, 7 Equipment Techs o7 years Manager, Test Engineering Deliver electrical testers for wafer/rowbar/die level TEL/Electroglas/Hitachi-Deco/Phasemetrics/In-house developed equipment 4 Programmers, 2 M.E.’s, 3 E.E.’s, 1 Device ... - 2017 Nov 02
... 8 Equipment Engineers, 7 Equipment Techs o7 years Manager, Test Engineering Deliver electrical testers for wafer/rowbar/die level TEL/Electroglas/Hitachi-Deco/Phasemetrics/In-house developed equipment 4 Programmers, 2 M.E.’s, 3 E.E.’s, 1 Device ... - 2017 Nov 02
Customer Service Engineer
Milpitas, CA, 95035
... Presented an idea of a new die design to reduce material loss by 20 percent as well as reduce process time by 30 seconds. Mechanical Engineering Intern, Greaves Cotton Pvt. Ltd., India. (2 months) June13-July13 Greaves Cotton is one of the biggest ... - 2017 Aug 24
... Presented an idea of a new die design to reduce material loss by 20 percent as well as reduce process time by 30 seconds. Mechanical Engineering Intern, Greaves Cotton Pvt. Ltd., India. (2 months) June13-July13 Greaves Cotton is one of the biggest ... - 2017 Aug 24
Sr.Packaging/Process Development, NPI - (Engineering Program Lead)
San Jose, CA
... Leader in the development of other types of packages using metal leadframe or laminate (ceramic or PCB) with thermal dissipation consideration,..QFN, COB, Chip scale, SiP, WLP, stacked die, MEMS/MOEMS, Laser projection module and flip chip (FC) with ... - 2017 Aug 07
... Leader in the development of other types of packages using metal leadframe or laminate (ceramic or PCB) with thermal dissipation consideration,..QFN, COB, Chip scale, SiP, WLP, stacked die, MEMS/MOEMS, Laser projection module and flip chip (FC) with ... - 2017 Aug 07
Market Intelligence, Strategy and Analytics
Fremont, CA
... QUALCOMM - STRATEGY San Diego, CA Marketing Manager December 2006-February 2008 • Performed Bill-of-Material and die cost analysis for various wireless and computing devices (smartphones, data cards, navigation devices, consumer devices). Created ... - 2017 Aug 04
... QUALCOMM - STRATEGY San Diego, CA Marketing Manager December 2006-February 2008 • Performed Bill-of-Material and die cost analysis for various wireless and computing devices (smartphones, data cards, navigation devices, consumer devices). Created ... - 2017 Aug 04
Director of ASIC Design
San Jose, CA
... • Develop and implemented pre-silicon die and power estimates for the IOs, memories and random logic power for 90nm and 65nm process nodes. • Evaluated vendors and foundries with low power libraries, memories and IOs with leakage and standby power ... - 2017 Jul 19
... • Develop and implemented pre-silicon die and power estimates for the IOs, memories and random logic power for 90nm and 65nm process nodes. • Evaluated vendors and foundries with low power libraries, memories and IOs with leakage and standby power ... - 2017 Jul 19
Engineer Desktop Support
Sunnyvale, CA, 94087
... Perform Die-Attach and Tip Attach. Perform set up, calibration and preventive maintenance task on test stations. Perform Pre-test, Tension, Temperature Cycle, Temperature Compensation, Jitter, Stressed Sensitivity, EEPROM and Final-test for the 30, ... - 2017 Jun 26
... Perform Die-Attach and Tip Attach. Perform set up, calibration and preventive maintenance task on test stations. Perform Pre-test, Tension, Temperature Cycle, Temperature Compensation, Jitter, Stressed Sensitivity, EEPROM and Final-test for the 30, ... - 2017 Jun 26