Director of ASIC Design

SOHAIL KHAN

Cell 408-***-**** • Home 408-***-**** **********@*****.***

SUMMARY

• Extensive experience in deep submicron (65nm, 40nm, 28nm) VLSI design, including hands-on technical and managerial experience with all phases of design from concept to production: product definition, architecture, logic design, synthesis, DFT/BIST, RTL, static timing analysis, physical verification, manufacturing test, and silicon bring up, silicon validation and debug.

• Demonstrated experience in building and managing ASIC Design Teams, design flow and tools, verification infrastructures.

• ASIC Design Methodology: experienced with the development of several successful top-down, timing-driven design flows, including software development, analog IP integration, system design & bring-up, integration of front-end and back-end VLSI design tools.

• Working knowledge and hands-on experience in chip power consumption estimation & projections and post-silicon correlation of Active and Leakage power estimates.

• Working knowledge of DDR2/DDR3, RLDRAM and Cache memories and digital controllers for complex memory architectures. Performance modelling of memory/cache architectures to optimize latency and identify performance bottlenecks.

• Hands-on experience in the design, implementation and verification of multi-level cache memory subsystems &controllers, DSP, Image Processors (ISPs), 4K Video scalers SOCs and 3D graphic processors.

• Working knowledge of FPGA design and emulation based on Synplicity and Xilinx P & R tools.

• Extensive experience with high-speed serial interfaces: HDMI, PCIe, eDP, Vby1 and LVDS protocols.

• Good familiarity with wireless OFDM architectures and design of 802.11 a/b/g/n products, Systemverilog, UVM methodology, coverage-driven verification flows, hardware implementation of DSP algorithms, Perl, C language and matlab.

EDUCATION

• Ph.D. Electrical and Computer Engineering, May 1995. University of Texas at Austin.

• M.S. Electrical and Computer Engineering, Dec 1990. University of Houston.

PROFESSIONAL EXPERIENCE

Director of ASIC Design, Marseille Networks, Inc., Feb’11-Present

Hands-on manager of the teams involved in the design and implementation of high performance of Video chips, from concept to mass production, targeted for consumer products such as Blu-ray players, set top boxes, streaming media devices, 4K cables and TVs. Taped out Three video ICs from specifications to final product release.

• Worked very closely with marketing to finalize the product definition. Developed and published the PRD for the highly integrated SOC and multi-media chips.

• Managed the design process from Concept to Silicon with extensive and comprehensive coordination and cooperation with ASIC, RTL Verification, FPGA emulation and hardware system teams.

• Technical chip lead: Develop and published the PRD, chip Architecture, chip design specifications, clocking and reset strategies, functional verification, physical implementation, software & system development, hardware virtualization and system bring up.

• Intimately involved with the development of the Chip specifications, micro-architecture of video processing blocks and Chip & module level verification test plans.

• Developed the architectural specifications and detail functional test plans for the design and implementation of SOC subsystem including the design and implementation of cache memory subsystems.

• Identified silicon proven analog Serdes and digital IPs. Managed the technical evaluations, negotiations, acquisition for the external IPs.

• Actively participated in the definition of product roadmap with technical Marketing and Executive Management. Developed and published details product schedule

• Interfaced with customers to resolve their technical hardware and software issues.

Director of Digital Design, SNS Logic Design, Fremont, CA Sept’08-Feb’11

• Responsible for all functions of Engineering: Project Management, Architecture, chip design, system design, embedded software development, QA, physical design, DFT, silicon bring-up, silicon validation and debug.

• Design, verification and implementation of digital controller for a mixed-signal high efficiency LED PWM chips with I2C/SPI/1-wire interfaces and phase shifted PWM/Analog dimming.

o Developed the detailed specifications and the microarchitecture of the dynamically adjustable phase shifter for multiply disabled LED strings. Designed and implemented the phaseshifter, SPI and dual-dimming modules.

o Designed, implemented and verified the duty extractor and Fader modules of the controllers.

o Post-Silicon bring-up and debug of the PWM chips for silicon validation of the chip functions.

• Design, implementation, integration and coverage-based functional verification for a mixed-signal ADSL chip. Specified, architected and integrated Serdes LVDS interfaces and DSP modules.

o Developed the uarchitecture of the framer, deframer, register, serializer and deserializer modules.

o Designed and implemented the design in RTL based on assertion.

Director of ASIC Design, Foveon, Inc., San Jose, CA Sept’07-Sept’08

Managed digital design and hardware engineering teams engage in the design and implementation of Image processing chips (ISPs) and image sensors in 65nm/40nm, digital controllers for image sensors, FPGA Emulation and test boards for phone camera modules.

• Responsible for all the phases of developing ISP ASIC design through complete product lifecycle, software development, architectural specification, algorithm implementation, RTL verification, FPGA emulation and physical implementation.

• Develop and implemented pre-silicon die and power estimates for the IOs, memories and random logic power for 90nm and 65nm process nodes.

• Evaluated vendors and foundries with low power libraries, memories and IOs with leakage and standby power controls to reduce overall power for high volume consumer devices.

Telairity Corporation, San Jose, CA Dec‘06-Sept’07

Sr. Development Engineer/Technical Manager

Design and implementation of a multi-core H.264 video processor consisting of five vector processors and IO cluster (25 million gates, 90nm/65nm CMOS technology).

• Designed and developed the DDR2/DDR3 memory controller and complex host interface for Vector Multiprocessor. Integrated the design in the chip level environment and verified by focusing & random testing the memory controller.

• Architected, design and implemented DDR parallel video ports for transferring video data. Verified the design on FPGA.

Intel Corporation July ’03 – Aug’06

Design Manager, P1265 Northrim Chip and Low Power Teams, Folsom, CA

• Mobile Logic lead for the design and development of Northrim ASIC chip (15 million gates, 1 million bits RAM, Dual DAC, on-chip PLL, DLL; 65nm CMOS technology).

o Staffed and formed an engineering team consisting of design, verification and physical design engineers.

o Managed the team for the design and development of the chip from architectural specification, micro-architecture definition, logic design and verification.

• Parallel responsibility for building and managing a multi-site Low Power team for power estimation, projection and correlation for Desktop and Mobile products.

o Staffed and managed a team (10 Engineers in US, 5 Engineers in India) for the architectural estimations, simulations and post-Si measurements of total active and leakage power.

o Led the effort for developing design flows and infrastructure for Total Power simulations, Total Design Power simulations for chipset & Graphics, core leakage optimization.

Intel Corporation July ’03 – July’05

Manager, Baseband Design Team, Wireless Products Division, San Diego, CA

Managed digital design team responsible for design and implementation of the PHY/MAC for 802.11 a/b/g/n Wireless products.

• Formed, managed and lead the silicon design team in implementing Baseband for 802.11 a/b/g/n designs. Identified, interviewed and recruited internal and external candidates for the formation of a Silicon Design Team. Conducted skill gap analysis and organized custom training programs for the team.

• Formed and lead the FPGA Task Group of WPD for the design and implementation of the Real Time Prototyping of the 802.11 a/b/g/n PHY and MAC layers.

• Led the effort for the design of a Multi-Channel FFT (MCFFT) to replace the individual FFT module in 2x3 MIMO 802.11n systems. Designed the input and output buffering and clocking schemes. The FFT team has proposed and designed a novel architecture for processing the even and odd samples in separate pipeline cores and reducing the processing latency by 50%.

• Implemented chip level synthesis based on Synopsys for Almagor (802.11 a/b/g Baseband) flow using top down and bottom up compile strategies for TSMC and P874 libraries.

• Developed hardware methodology and implementation guidelines for enabling Extensible RTL building blocks across WPD/WNG/ICG product groups. Developed and implemented the modular hardware extensibility and reusability criteria for design of RTL modules.

• Spearheaded the planning, Initiation, installation and bring-up of the complete Ardon2 Design database.

Sr. Design Engineer, Micron, Inc. April ‘99-Mar ‘03

• Developed and implemented infrastructure/flow for Synthesis, Physical Synthesis (Physical Compiler) and Static Timing Analysis for a 250 MHZ 20 Mbit Ternary CAM design in 0.13-micron, (330 mm2 area).

• Closely interfaced with the back-end team to floorplan and route the chip for timing closure. Identified and fixed the critical paths by restructuring the logic, modifying the floorplan and timing constraints for physical synthesis to meet timing goals.

• Developed and implemented the clocking strategy for the chip. Specified the Delay Locked Loop (DLL) requirements and evaluated various floorplans to determine the best clocking strategy.

• Modified, restructured and verified the FPGA memory controller for RLDRAM I & II to work with RLDRAM II memories. Implemented the design on XC2V1000-6BG575 Xilinx.

• Defined the architecture and implemented multi-mode DDR I & II external memory controller.

• Lead the effort for overall and incremental integration/design and verification of a SOC chip, which integrated a high performance graphic processor, North and South Bridge, arbitration modules and DDR memory controller.

• Developed and specified the microarchitecture of the texture cache for a high performance graphic processor.

Member of Technical Staff, Poseidon Technology, Inc. OCT’98 – APR’1999.

Poseidon was developing X86 server chipset solution. Developed detailed specifications and timing requirements of the Memory Interface Controller. Design and implemented a highly pipelined micro architecture with separate interfaces for command and data routing.

Sr. Design Engineer, Texas Instrument, Inc., Texas. JUN’95 – OCT’98

• Specifications, logic and circuit design of a dual cache/program memory controller for TMS320C6202 DSP to permit concurrent accesses by DMA and CPU to multiple banks of program/cache memory.

• Identified and improved the timing of critical paths to achieve 250 MHz. Restructured VHDL code and chip/module hierarchy to achieve timing goals for the dual cache controller and the chip.

• Developed product requirements for DSP TMS320C6202 using Panther 0.18 um gate array components by migrating DSP TMS320C6201 to the new technology library.

• Identified and assessed performance requirements for DSP TMS320C6202 memories, floorplan, clocking strategies and PLL.

• Designed and developed specifications and architecture of the High Performance Timing processor.

• Defined micro-architecture for the datapath. Designed, implemented and optimized the datapath, I/O interfaces and detailed instruction decoder for processor to work at 200 MHz.

• Developed and implemented cache/memory architectural and performance behavioral models.

• Specified the cache architecture and developed specifications. Developed and implemented RTL for the configurable cache using VHDL.

• Performance evaluation and characterization of memory accesses for various cache/memory configurations and identified the source(s) of loads and stores that cause cache misses

• Developed System Architecture Reference (SAR), the foundation of the TMS470R1x family of microcontrollers based ARM7 core.

PUBLICATIONS

1) Mohammad S. Khan and E.E. Swartzlander, Jr., "Design and Implementation of an Interface Control Unit for Rapid Prototyping," Fourth International Workshop on Rapid System Prototyping, June 28-30 1993, Research Triangle Park, North Carolina, pp.141-148.

2) Mohammad S. Khan and E.E. Swartzlander, Jr., "A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors," International Symposium on Circuits and Systems, June 12-14 1994, London, UK.

3) Mohammad S. Khan and E.E. Swartzlander, Jr., "An Asynchronous Communication Protocol for Heterogeneous Digital Signal Processors," 37th Midwest Symposium on Circuits and Systems, Lafayette, Louisiana, August 3-5 1994.

4) Mohammad S. Khan and E.E. Swartzlander, Jr., "Rapid Prototyping Fault-Tolerant Heterogeneous Digital Signal Processing Systems," Fifth International Workshop on Rapid System Prototyping, June 2-5 1995, Research Triangle Park, North Carolina.

5) Mohammad S. Khan," Design and Implementation of an Interface Control Unit for Rapid Prototyping," Chapter 8 in Application Specific Processors (E.E. Swartzlander, Jr., editor), Kluwer Academic Publishers, Boston, 1996 (in press).

6) Mohammad S. Khan and E.E. Swartzlander, Jr., " Rapid Prototyping of Heterogeneous Digital Signal Processors," Thirtieth Annual Asilamar conference on Signals, Systems, and Computers, Nov 4-6, 1996.

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