Software Engineer Computer Engineering

SRIMAYEE KANAGALA www.linkedin.com/in/srimayee-kanagala

MS Computer Engineering (Thesis) ********@***.*** 480-***-**** Summary

Graduate student specializing in Deep Neural Networks and their implementation on Hardware Accelerators. 5+ years expertise in hardware programming.

Education

MS in Computer Engineering (Summer 2020)

Specialization: Deep Learning, Hardware Acceleration, System-level design of DNNs, AI, Computer Architecture Arizona State University, AZ

BE in Electronics and Communication Engineering Spring 2012 JNTUH, India

Skills

• Languages: Python, C++, C, MATLAB, Tcl, Perl, Shell, System Verilog, Verilog, VHDL

• Frameworks: Tensor Flow, OpenCV, Pytorch, Numpy, Scipy, TensorRT

• Tools: Xilinx SDx, Xilinx HLS, Xilinx Vivado Design Suite, Cadence IES, Synopsys VCS, Mentor Graphics Questa Sim, MATLAB Simulink, MATLAB Stateflow, Jupyter Notebook, Pycharm, Gem5

• Boards: ZCU102, ZC706, U200 and U280(Data Cards for Acceleration), Nvidia Jetson Nano Work Experience

Research Assistant, WISCA lab, ASU Spring19 - Present

• Developed a programmable accelerator for linear algebra techniques using Systolic Architecture. Implemented both fixed point and floating point designs targeted on Xilinx FPGA.

• Designed a folded architecture programmable for nxn matrices upto n=32. Software Intern, Xilinx, San Jose, CA Summer 2019

• Developed tools for verification of Xilinx Sdx for hardware acceleration for Alveo data cards. Worked extensively on Xilinx Run Time (XRT) and DSA.

• Worked on ML-Suite for Xilinx Alveo Data Cards in accelerating an object detection algorithm. Software Engineer I & II – Xilinx, India Summer 2013 - Summer 2018

• Wrote highly maintainable, solid code in System Verilog for verification of Vivado Simulator and has won consistent praise from subsequent developers since initial version.

• Drove verification of System Verilog features such as Interfaces, Random Constraints, Functional Coverage, Classes, Assertions covering almost 90% of the LRM.

• Prepared test plans and developed test cases based on PRs for Vivado Simulator targetting SV,Verilog,VHDL, SystemC, cross language support, debugging features on simulator, emulation using Qemu etc.

• Worked with project managers, developers and customers to resolve simulator and design issues especially related to AXI IPs exhibiting strong HDL skills.

• Worked on performance benchmarking and profiling of hardware acceleration for Vivado SDx. Academic Projects

RGBD Semantic Segmentation using CNN and GNN on Nvidia Jetson Nano Fall 2019

• Compared the performance of CNN, D-CNN and GNN for depth aware semantic segmentation.

• Implemented inference on Jetson Nano and achieved a performance of 1.34x in GNN and D-CNN compared to CNN. Deep Deterministic Policy Gradient Algorithm for a Self-Driving Car on TORCS simulator Spring 2019

• Implemented Reinforcement Learning for a self-driving car using Deep Deterministic Policy Gradient algorithm on TORCS simulator. Used Python and Tensorflow.

CNN for Sentence Classification Spring 2019

• Implemented CNN models for sentence classification on SST2 dataset using pre-trained model of Google's Word2Vec.

• The accuracy achieved was 89.76% on CNN static variant where the word vectors were not updated and 88.53% on CNN non static variants where the word vectors were updated for each epoch 3D hand pose estimation and classification for hand pose estimation using CNN Fall 2018

• Implemented the Pixel wise 3D dense regression algorithm by extracting the features of both 2D and 3D depth-maps of segmented images from MSRA and NYU dataset.

• The estimated poses are classified using multi-class classifiers such as SVM_OVO, Bernoulli NB etc. FPGA implementation of k-means clustering algorithm Fall 2018

• Designed a hardware accelerator for k-mean clustering algorithm targeted on ZCU102. Implemented unfolding and interleaving techniques to increase performance. Achieved a 20x speed increase in the performance

Contact this candidate