Gopikrishnan Raveendran Nair

**** * ********** ** ***** AZ-85281 858-***-**** www.linkedin.com/in/gopikrishnanr adem2l@r.postjobfree.com

SUMMARY

Computer engineering graduate student specializing in computer systems with work experience as RTL design engineer, looking for full time positions from summer 2020.

EDUCATION

MS, Computer Engineering May 2020

Arizona State University, Tempe GPA 3.74/4

Bachelor of Technology, Electronics and Communications April 2014 Kerala University, India GPA 7.21/10

COURSES

Foundations of Algorithms, Digital Systems and Circuits, Embedded Systems programming, Computer Architecture, Constructionist approach to microprocessor design, VLSI design, System Level Design for Multicore Architectures. TECHNICAL SKILLS

• Expertise in digital design.

• Programming languages: C++, Verilog, System Verilog,perl.

• DevOps tools: SVN, Jira, GitLab.

• Interfaces: GPIO, SPI, I2C, AXI .

• Boards: Zynq 7035 SOC, Intel Quark Galileo board, Spartan 6, Xilinx Virtex.

• Design Tools: Xilinx Vivado & Chipscope, Xilinx ISE 14.6, Innovus, Synopsys Design compiler, Hspice, Modelsim, Matlab, Cadence Virtuoso, Synopsys PrimeTime, IC validator(DRC & LVS) PROFESSIONAL EXPERIENCE

RTL Design Engineer, Westghats Technologies, India Aug 2014-June 2018

• Designed and implemented OpenVX functions in Verilog to cover common functionality required by vision applications.

• Re-designed the DMA architecture which resulted in more efficient memory utilization and reduced data processing times.

• Designed and implemented real time edge detection, face detection, feature extraction and color conversion algorithms used for image segmentation and object detection in smart camera

• Worked collaboratively with the software team for prototyping the design in FPGA.

• Implemented a BFM for AXI protocol for verification of design. INTERNSHIP

FPGA Engineer, LITEPOINT, San Jose May 2019-Aug 2019

• Implemented a new module using Verilog in the FPGA design to calculate the fan speed in the existing BAJA products.

• Debugged the flash memory read which causes the FPGA inside the MW products to hang using chipscope.

• Added GitLab support for the FPGA builds to automate the FPGA build and testing.

• Added logic to handle the new inputs in the FPGA design to support the board revision change. ACADEMIC PROJECTS

RTL to GDS II ASIC design: Dot product and Square Root engine Nov 2019

• Designed and implemented a pipelined 256 input dot product and square root engine Verilog.

• Performed floor planning, power planning and clock tree synthesis using Cadence Innovus.

• Post layout timing and power analysis performed using prime time. Hardware design of microcode engine using Verilog May 2019

• Designed and implemented the control and datapath logic of a simple multicycle microprocessor.

• Can perform add, sub, less than, greater than, accumulate and no-op instruction. Signature based hit predictor cache replacement policy in gem5 simulator Feb 2019

• Implemented SHiP based cache replacement policy in Cpp and simulated it in gem5 simulator. Hardware design of LIFO, FIFO, FIR filter and simple ALU Feb 2019

• Designed and implemented LIFO, FIFO, FIR filter and ALU using Verilog and verified the design using testbenches. Design of a 16x16 RF bit cell with 1 read and 1 write port Oct 2019

• Designed a 16x16 RF bit cell and 4-16 decoder using 7nm technology. Design is optimized for low area and high frequency. DRC, LVS and post layout simulation are done to verify the design.

Contact this candidate