Designer Manager

MINH (MIMI) NGUYEN

Email: adfwm6@r.postjobfree.com

Mobile: 480-***-****

OBJECTIVE

Senior Layout Designer / Mask Designer

EDUCATION

Mesa Community College Mesa, Arizona

Associate of Applied Science in Electronic-Mechanical Drafting Technology June 1993

Intel Corporation Chandler, Arizona

Certificate of Completion Mask Design Training course at Intel (~200 hrs) December 1995

SUMMARY OF QUALIFICATIONS: Layout Designer

20+ years of Layout Designer experienced from device creation, creating test rows, to Full chip integration.

7nm Tri-Gate/FinFet High Speed Experience

Knowledge of 28nm, 22nm, 14nm, 10nm process and TSMC Library.

Floor planning on large and complex Blocks.

Proficient with layout techniques such as common centroid, interdigitation,

device matching, isolation, shielding, using dummy devices.

Layout team leadership.

Proficient in all Windows application such as Word, Outlook, Excel and PowerPoint.

EXPERIENCE

Intel Corporation - Foundry Design Kits Chandler, AZ

Layout Designer (Intel Contact Employee) 8/2016 – 8/2018

Physical layout of Digital and Analog circuits utilizing Virtuoso 6.1.6 and Genesys.

Verify design using Calibre and PDS.

Working with IDV team on P1222, P1273, P1275 - 14 nm, 10nm process.

Creating Library cells, test rows for DRC abutment verification.

Create wrappers and verify all new IDV to release specs.

Intel Corporation - Intel Custom Foundry and Intel Labs Hillsboro, OR

Layout Designer (Intel Contact Employee) 7/2013 – 7/2015

Perform full custom layout for 14nm FinFET process by using Cadence 6.1.6

Using Calibre for LVS/DRC Verifications.

Took top-level blocks ownership, plan power grid, pins and routing down to sub-blocks and create sub-blocks as needed.

Working with project lead to debug DRC before tape out.

Perform full custom Layout for Intel Labs group on 14nm Test Chip, Assembly and Floor Planning on Cells,

Blocks, Clusters by using Intel Genoa Layout Tool and CPDS Hercules for Verification.

1/2013 – 7/2013 Took Voluntary Separation Package from Intel to pursue other opportunities. Eligible for rehire.

Intel Corporation – Hard IP Group Chandler, AZ

Layout Designer/Mask Designer 8/2008 – 1/2013

Experienced with designing layouts of highly complex RF/ Analog, IC Mixed Signal, High-speed analog circuits, Serdes Architecture,

Pwr. Management and Audio layout using various technologies – 22nm, 28nm, 32nm, 40nm, 45nm, 65nm, 90nm and 180nm Technology on family of system-on-a-chip (SoC) products.

Physical layout of Digital and Analog circuits utilizing Virtuoso VXL and Genesys.

Verify design using Calibre, Hercules LVS, PDS and RV tool sets.

Floor planning and power grid planning.

Took Cluster ownership on multiple project: Manzano, Concan ….

Assist and mentor junior Mask Designer.

Lead 3-5 people and maintain the schedule for whole Cluster.

Using APR Tools: Helix, Alpie, for Floorplan / Placement and Routing.

Marvell Corporation – X Scale Chandler, AZ

Layout Designer/Mask Designer 11/2006 – 8/2008

Responsibilities included core ownership, multiple cluster ownership and DRC/LVS verification using Calibre verification

for Xscale core processors.

Working on TSMC Library custom cells, including the tracking of layout progress and insuring all cells met layout guidelines.

Work closely with circuit design engineers on various digital and analog layout using Cadence Virtuoso and Laker.

Verify design using Calibre tool sets.

Intel Corporation – Hard IP Chandler, AZ

Layout Designer/Mask Designer 5/1995 – 11/2006

Floor planning and power grid planning on Unit level of hierarchies.

Physical layout of Digital and Analog circuits utilizing the DLS, Genesys and Virtuoso XL.

Verify design using Hercules LVS, PDS and RV tool sets.

Setup weekly Layout Review for Unit level.

REFERENCES:

Dan Burres, Intel Mask Design Manager 480-***-****

Yuyun Liao, Intel Manager 503-***-****

Andrea Willis, Intel Senior Mask Designer 480-***-****

Contact this candidate