ROHAN SHASTRI

adc7qw@r.postjobfree.com 480-***-**** www.linkedin.com/in/shastrirohan

ELECTRICAL ENGINEER

Graduate student working towards master’s degree in Electrical Engineering with around 4 years of work experience in Information Technology and currently seeking full-time job opportunities in the field of Physical/Hardware Design.

EDUCATION

Masters of Science in Electrical Engineering May’20

Arizona State University, Tempe, AZ GPA – 3.30/4.0

Courses: Digital Systems and Circuits, VLSI Design, Hardware Acceleration and FPGA, Constructionist Approach to Microprocessor Design, Neuromorphic Computing Hardware Design, Python for Rapid Engineering Solutions

Bachelors of Technology in Electronics and Telecommunications Engineering May’14

Shri Guru Gobind Singhji Institute, Nanded, Maharashtra, India GPA – 7.36/10.0

TECHNICAL SKILLS

Programming languages – Python, System Verilog, Perl, C

Tools/Simulators/OS – Cadence Virtuoso Schematic and Layout editor, 7nm and 32nm PDK, Mentor Graphics Calibre nmDRC/LVS/PEX, Cadence Spectre, HSPICE, Waveviewer, MATLAB-Simulink, Synopsys Design Compiler, Cadence Innovus APR, ModelSim, StarRC, Spyder, Genesis2, Synopsys VCS, Synopsys Primetime, Windows, Linux

ACADEMIC PROJECTS

Energy efficient custom hardware using 7nm ASAP7 PDK for MNIST handwritten digit recognition, ASU Spring’20

Trained a Multi Layered Perceptron with an accuracy of above 98% using binary neural networks with both weights and activations having binary values of +1 and -1.

Generated synthesized netlist from behavioural Verilog RTL and performed APR.

Design of Sequential Square Root, ASU Fall’19

Built a Sequential Square Root in System Verilog which would output the square root of a random fixed point 16-bit number every 16 cycles by using appropriate ready-valid handshaking signals.

Generated and synthesized the RTL design using Genesis2 and Synopsys Design Compiler and verified the results in ModelSim.

Developed a test bench for design verification with a gold model and test plan for all possible test cases.

RTL to GDSII: Convolution and Average Pooling Engine Design using 7nm ASAP7 PDK, ASU Spring’19

Designed the convolution module by considering the number of parallel adders and multipliers and developed a Verilog code to compute the convolution of 4x4 RGB image with a 3x3 kernel and verified the functionality in ModelSim.

Performed DC synthesis and APR using Innovus and verified the DRC and LVS in Cadence Virtuoso after exporting the gds file

Performed gate level static timing analysis and used PrimeTime to extract average power.

Designed the system at 1500ps with positive slack and reported the top 5 critical paths.

Optimized the design for the quality metric : (Total Latency)2 x Power x Area

Design of 4-to-16 Decoder and 16x16 RF Array using 7nm ASAP7 PDK, ASU Spring’19

Built the layout of 4-to-16 decoder using 2-to-4 decoder and NAND logic with gate sizing obtained by calculating logical effort.

Performed pre-layout simulation by generating netlist from virtuoso CDL and verified the read and write functionalities.

Designed schematic and layout of RF bit cell using RVT device model and obtained clean DRC and LVS pass.

Performed post-layout simulation and verified functionality with PEX netlist using xACT 3D.

Reported the fastest and slowest corner cases along with maximum operating frequency and optimized the area and performance of 16x16 RF array.

Design of High Performance 4-to-1 IF Neuron using 32nm PDK, ASU Fall’18

Built the schematic and layout of IF neuron using 4-bit adder, 5-bit adder, D Flip Flop, AND and OR logic gates using Cadence Virtuoso and verified the DRC and LVS.

Verified the functionality by writing testbenches using generated netlists.

Built the adders using mirror structure of 1-bit full adder and designed MUX based D Flip Flop using transmission gates.

WORK EXPERIENCE

Cognizant Technology Solutions, Bangalore, India Nov’14 – Jul’18

Associate

Developed interactive BI dashboards using TIBCO Spotfire and scripting languages like Python, R and JavaScript.

Wrote SQL queries, materialized views and stored procedures to manipulate database.

Developed a proof of concept IoT based Android mobile application named Connected Vehicle Accelerator using Ionic Framework for creating, testing and deploying Fast Data to be used by Insurance providers.

Created POCs, design documents, test scripts and presentations for high level understanding of projects.

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