Engineer Design

NILAY AJAYKUMAR SHAH

*: B /**, Deep Apartment; Near, R. C. Patel School; Vasna, Ahmedabad-

380007, Gujarat, India.

:: ****.******@*****.***, ***********@*****.*** (: (R) 079-********, (M)

090********

OBJECTIVE

In quest of a challenging position in the organization that offers me

generous opportunities to explore & outshine in the field of IC Layout

Design Engineer while accomplishing personal, professional as well as

organizational goals.

EDUCATIONAL QUALIFICATIONS

WORK EXPERIENCE

BROADCOM Mumbai, India

February-2012-Present

Engineer-IC Design

I had developed bit-cell of Multi Port Register File Compiler in

16nm Technology. I had developed Dual Port & Multi Port Register File

Compiler in 28nm Technology. I have developed 20nm Standard Cell Library.

Net Logic Semiconductor Pvt. Ltd, Mumbai, India (1 Year 7 month)

July 2010-February-2012

Layout Design Engineer

I have joined Net Logic Semiconductors as a Layout Engineer (Trainee)

on July 2010. I have joined Net Logic as a permanent employee on Jan 2011.

I have worked with 28nm Technology group.

. Worked on two 28nm project, which has been taped out successfully.

They were working on Silicon. My work includes:

1) Layout design for 14-tracks, 11-track and 8-tracks Std Cell

Library Design

2) Layout design for Clock Buffer Library Design

3) Layout design for High Speed & Low Speed Register File Compiler

I am responsible for delivering high quality layout for different

group like 45nm Technology.

PROJECTS

. Universal Asynchronous Receiver and Transmitter (At C-DAC)

. High Angular Resolution For Absolute Angle & Incremental Angle Encoder

Reader For Astronomy Telescope System (At PRL) ( 8th Semester in B.E.)

. Temperature Indicator cum Controller (7th Semester in B.E.)

COMPUTER KNOWLEDGE

Languages : VHDL, Verilog.

IC Layout Design : Micro Wind, Cadence(Virtuoso), Laker basic

Tool knowledge

OS : Windows, Linux overview

Scripting Language : Basic knowledge of Skill

EXTRA CURRICULAR

. Secured 3rd position in the Late Shree Chandrakant Shah Memorial Skating

Championships on 22nd June 2003 at Pritamnagar - Ahmedabad.

. Secured first rank in the exam of SANTOOR instrument on 5th July 2001.

PERSONAL DETAIL

Birth Date 27th June 1988

Marital Status Single

Languages known Gujarati, Hindi, English

Degree University / Board / Percentage / Grade Year

Institute

PG-DVLSI C-DAC A 2010

B.E.(E & C) Gujarat University 65.22 2009

H.S.C. G.H.S.E.B. 68.00 2005

(Science)

S.S.C. G.S.E.B. 82.57 2003

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